CS4812 Cirrus Logic, CS4812 Datasheet
CS4812
Related parts for CS4812
CS4812 Summary of contents
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... P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com Description The CS4812 is a complete audio effects processing system on a chip. This device includes a proprietary 24- bit audio processing engine with considerable on-chip RAM, two ADCs and two DACs. A full-featured serial control port allows interfacing to an external host microcontroller ...
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... A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com Master Mode ................................................................................. Slave Mode ................................................................................... Master Mode ................... Slave Mode ..................... 16 CS4812 DS291PP3 ...
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... Figure 23.Control Port Timing Figure 24.I C Slave Mode Read Flow Diagram ....................................................... 25 2 Figure 25.I C Slave Mode Read Flow Diagram with DSP REQ ............................... 26 Figure 26.HostBoot Flow Diagram ........................................................................... 27 Figure 27.CS4812 Suggested Layout ...................................................................... 28 Figure 28.Pin Assignments ...................................................................................... 29 DS291PP3 2 C Master Mode AutoBoot ..................................... Slave Mode Write .............................................. Slave Mode Write ...
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... VA 5V Full Scale Input Sine wave, A Symbol Stereo Audio channels (A weighted, Note 5) (unweighted, Note 5) (Note 1,5) THD+N (Note 1,2,5) (Note 6) (Note 2) (Note 2) CMRR (Note ∆t gd -3dB (Note 3) -0.14dB (Note (Note 3) rms = 15/48 kHz = 313 µs. gd CS4812 Min Typ Max Units Bits 93 100 - -92 - -92 - ...
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... DS291PP3 (T = 25° Full Scale Output Sine wave, A Symbol (DAC not muted, A weighted) THD+N (Note 7) (Note 7) (Differential) (Note 2) (Fs/2 to 2Fs, Note CCIR-2K (Note 8) (1 kHz Note 2) rms CS4812 Min Typ Max Units Bits 95 100 - dB - -90 - ...
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... XTI Frequency XTI = 128Fs, 256Fs, 512Fs XTI Duty Cycle XTI = 128Fs, 256Fs, 512Fs XTI Jitter Tolerance RST Low Time Notes: 9. Guaranteed by characterization but not tested. 10. On power-up, the CS4812 RST pin should be asserted until the power supplies have reached steady state °C; VA +5V, C ...
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... CS4812 Max Unit 6 MHz - 100 ns 100 µs - 2*DSPCLK+10 ns 100 ns 100 ns 7 ...
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... CS4812 * DS291PP3 ...
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... CS4812 Typ Max Units Fs - kHz 1/(2*Fs 1/(2*Fs µ µ µ 100 ...
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... RST rising to start condition SDA Hold Time from SCL Falling Rise Time of Both SDA and SCL Fall Time of Both SDA and SCL SCL Falling to CS4812 ACK SCL Falling to SDA Valid During READ Time from SCL Rising to REQ Rising Rise Time for REQ ...
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... DS291PP3 CS4812 * 11 ...
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... Repeated t cldv t high t hdst sud t sust low hdd 2 ® C Control Port Master Mode (AutoBoot) Timing CS4812 2 ® C MASTER (T = 25°C; A Min Typ Max - 1/(2*Fs 1/(2*Fs 250 - - ...
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... Applied) Symbol Digital VD Analog °C; VA 5V) A Symbol (except XTI) V (except XTI -2.0 mA (except XTO 2.0 mA (except XTO (XTI) V (XTI) V (Digital Inputs) (High-Z Digital Outputs) Symbol CS4812 Min Typ Max -0.3 - 6.0 -0 ±10.0 -0.7 - (VA)+0.7 -0.7 - (VD)+0.7 -55 - +125 -65 - +150 Min Typ Max 4.75 5.0 5.25 4 ...
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... RESET 41 PIO0 40 Control/ PIO1 Monitor 37 PIO2 Circuitry 35 PIO3 AGND1..4 DGND1.. Ω S All unused inputs should be tied to ground. CS4812 Ferrite Bead + µ F 0.1 µ 1..2 7 AOUT1+ ANALOG 8 FILTER AOUT1- 9 AOUT2+ ANALOG 10 FILTER AOUT2- 14 RES-NC 15 RES-NC ...
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... RST Circuit 73 PLLEN RESET Figure 6. Typical Connection Diagram, Control Port Master Mode 63 SCL/CCLK 62 SDA/CDOUT SPI 68 AD0/CS EEPROM 67 AD1/CDIN 71 REQ VD 69 SPI/I2C 70 SCPM Reset RST Circuit 73 PLLEN RESET Figure 7. Typical Connection Diagram, Control Port SPI Master Mode CS4812 CS4812 CS4812 15 ...
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... MICRO CONTROLLER MOSI GPIO RESET D CIRCUIT VD Figure 9. Typical Connection Diagram, Control Port SPI Slave Mode CS4812 CS4812 SDA/CDOUT SCL/CCLK CLKOUT AD0/CS AD1/CDIN REQ SPI/I2C SCPM/S RST PLLEN CS4812 SDA/CDOUT SCL/CCLK CLKOUT AD0/CS AD1/CDIN REQ SPI/I2C SCPM/S RST PLLEN DS291PP3 ...
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... FUNCTIONAL DESCRIPTION 3.1 Overview The CS4812 is a complete audio subsystem on a chip, integrating an DSP with on-chip RAM, two 24-bit ADCs, two 24-bit DACs, and a serial control port. The sigma-delta ADCs include linear phase digital anti-aliasing filters and only require a single-pole external passive filter. ...
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... Digital High Pass Filter In DC coupled systems, a small DC offset may ex- ist between the input circuitry and the A/D convert- ers. The CS4812 includes a defeatable high pass filter after the decimator to remove these DC com- ponents. The high pass filter response is given in “High Pass Filter Characteristics” on page 4 and scales linearly with sample rate ...
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... CDIN, the control data input, is the serial data input line to the CS4812. CDOUT, the control data output, is the output data line from the CS4812 open-drain and requires a 2.2 kΩ pull-up resistor. CS, the chip select signal, is asserted low to enable the SPI port ...
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... CLKOUT. CCLK and CS may be inputs or outputs with respect to the CS4812. If the serial control port of the CS4812 is defined as the master, then CCLK and CS are outputs and CCLK requires a 2.2 kΩ pull-up re- sistor. If the CS4812 is defined as the slave, then CCLK and CS are inputs and no pull-up resistor is re- quired on CCLK ...
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... In SPI slave mode, a read sequence from an exter- nal controller is shown in Figure 17. The host con- troller executes a partial write-cycle by sending a 16-bit write preamble to the CS4812 with the MAP byte set to the address of the control port byte reg- ister to be read. The host controller then de-asserts CS, re-asserts CS, and sends the 7-bit chip address followed by the R/W bit set to 1 ...
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... INCR bit in the MAP byte. During a write sequence, multiple bytes may be written by continuing to send data bytes to the CS4812 after the first data byte and before de-as- serting CS. If auto increment is disabled, the last data byte sent will appear in the register designated by the MAP ...
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... C device address. SCL may be defined as an input or an output with respect to the CS4812. If the serial control port of the CS4812 is defined as the master, then SCL is an open-drain output and requires a pull-up resistor as shown in Figure 5. Conversely, if the serial control port of the CS4812 is defined as the slave, then SCL is an input ...
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... Figure 22.. The host controller sends a write preamble consisting of a start condition followed by the slave address for the CS4812. The slave address byte consists of a 7-bit address field (00100|AD1|AD0) followed by a Read/Write bit (set to 0). AD1 and AD0 correspond to the logic levels applied to the these pins on the CS4812 ...
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... INCR bit in the MAP byte. During a write sequence, multiple bytes may be written by continuing to send data bytes to the CS4812 after the first data byte and before initiat- ing a stop condition. If auto increment is disabled, the last data byte sent will appear in the register designated by the MAP ...
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... MAP. N During a read sequence, multiple bytes may be read by continuing to clock in data bytes to the CS4812 after the first data byte and before initiating a stop condition. If auto increment is disabled, the last data byte read will be the register designated by the MAP ...
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... Section 1.2.1 of AN195 for an example of a host boot sequence. 3.7 Resets There are several reset mechanisms in the CS4812 which affect different parts of the chip. Full chip re- set can only be achieved by asserting the external RST pin. With RST asserted, the chip enters low ...
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... When using separate supplies, the analog and digi- tal power should be connected to the CS4812 via a ferrite bead, positioned closer than 1" to the device (see Figure 21). The CS4812 VA pin should be de- rived from the quietest power source available. If Digital Power ...
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... CS4812 89 90 100-PIN MQFP 100 Figure 28. Pin Assignments CS4812 VD DGND SCL/CCLK SDA/CDOUT RES-NC RES-NC RES-NC RES-NC RES- RES-DGND ...
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... The load on CMOUT must be DC only, with an impedance of not less than 50 kΩ. CMFILT+,CMFILT- - Common Mode Filter Connections Inputs: These pins are connections for external filter components required by the internal common mode reference circuit. See the typical connection diagram in Figure 5. for details. 30 CS4812 DS291PP3 ...
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... The control port can not be accessed when reset is low. DS291PP3 2 C format if tied SPI format if tied to DGND. mode, AD0 is an input and defines bit 0 of the partial chip address. The upper 5 mode, SDA is the bidirectional data I/O line. In SPI mode, CDOUT is the serial CS4812 2 C mode. In SPI mode ...
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... These pins are reserved and must be tied to VD for normal operation. RES-DGND - Reserved, Connect to DGND These pins are reserved and must be tied to digital ground for normal operation. RES-AGND - Reserved, Connect to AGND These pins are reserved and must be tied to analog ground for normal operation. 32 CS4812 DS291PP3 ...
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... The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units are in volts. DS291PP3 CS4812 33 ...
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... CS4812 A A1 MILLIMETERS MIN MAX --- 3.400 0.250 0.350 0.220 0.380 16.950 17.450 13.900 14.100 22.950 23.450 19.900 20.100 0.550 0.750 0.00° ...
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Notes • ...
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