CS18LV10245 CHIPLUS, CS18LV10245 Datasheet

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CS18LV10245

Manufacturer Part Number
CS18LV10245
Description
HIgh Speed Super Low Power SRAM
Manufacturer
CHIPLUS
Datasheet

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Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of
4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed, super low power features and maximum access time of 55/70ns in 5V operation. Easy
memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable
(/OE).
significantly when chip is deselected. The CS18LV10245 is available in JEDEC standard 32-pin
sTSOP - I (8x13.4 mm), TSOP - I (8x20mm), SOP (450 mil) and PDIP (600 mil) packages.
1.
2.
3.
4.
5.
CS18LV10245CC
CS18LV10245DC
CS18LV10245EC
CS18LV10245LC
CS18LV10245CI
CS18LV10245DI
CS18LV10245EI
CS18LV10245LI
Note: Green package part no, sees order information.
Copyright
DESCRIPTION
FEATURES
Product Family
The CS18LV10245 has an automatic power down feature, reducing the power consumption
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Ultra low power consumption :
Standby Typ. = 0.50uA, (Typical value @ Vcc = 5.0V, TA = 25
Standard pin configuration
Part No.
The CS18LV10245 is a high performance, high speed and super low power CMOS Static
2.0V (min) data retention
Low operation voltage : 4.5 ~ 5.5V ; 5mA@1MHz (Max.) operating current (Vcc = 5.0V)
32 - SOP 450mil
32 - sTSOP-I - 8X13.4mm
32 - TSOP-I 8X20mm
32 - PDIP 600mil
2004 March Chiplus Semiconductor Corp. All rights reserved.
Operating Temp Vcc. Range Speed (ns)
-40~85
128K-Word By 8 Bit
0~70
High Speed Super Low Power SRAM
o
C
o
C
4.5 ~ 5.5
55/70
0
Standby (Typ.)
C)
0.50uA
0.80uA
CS18LV10245
32 SOP
32 STSOP
32 TSOP (I)
32 PDIP
32 SOP
32 STSOP
32 TSOP (I)
32 PDIP
Package Type
.
Rev. 1.2
P 1

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CS18LV10245 Summary of contents

Page 1

... By 8 Bit DESCRIPTION The CS18LV10245 is a high performance, high speed and super low power CMOS Static Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of 4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed, super low power features and maximum access time of 55/70ns in 5V operation ...

Page 2

... High Speed Super Low Power SRAM 128K-Word By 8 Bit PIN CONFIGURATIONS 32 SOP 450 mil 32 PDIP 600 mil BLOCK DIAGRAM Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. CS18LV10245 32 STSOP 8x13.4mm 32 TSOP(I) 8x20mm . Rev. 1 ...

Page 3

... Selected X Output H Disabled Read H L Write Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. /CE CE2 / CS18LV10245 Function DQ0~7 Vcc Current High Z I CCSB High Z D OUT CCSB1 Rev. 1 ...

Page 4

... IN C Input/Output Capacitance DQ 1. This parameter is guaranteed and not tested. Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. Parameter Ambient Temperature o 0~ -40~ ( =1.0 MHz) Conditions V CS18LV10245 Rating -0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20 Vcc 4.5V ~5.5V 4.5V ~ 5.5V MAX = =0V I/O Unit V O ...

Page 5

... Test Conduction /CE≧V -0.2V -0. ≧ /CE≧V -0.2V -0. ≧ See Retention Waveform = Read Cycle Time. RC CS18LV10245 (1) MIN TYP MAX -0.5 0.8 2.0 Vcc+0 0.4 2.4 (3) 35 MAX (1) MIN TYP MAX Unit 1.5 ≦ ...

Page 6

... Timing Reference Level Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. INPUTS Must be standby Will be change from May change for Change state unknown Center line is high impedance “OFF” state Vcc/0V 5ns 0.5Vcc CS18LV10245 ( /CE Controlled ) ( CE2 Controlled ) OUTPUTS Rev. 1 ...

Page 7

... Chip Deselect to Output in High Z (CE2) EHQZ CHZ2 t t Output Disable to Output in High Z GHQZ OHZ t t Out Disable to Address Change AXOX OH Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved Description CS18LV10245 Vcc = 5.0V ) -55 -70 MIN MAX MIN MAX ...

Page 8

... VIL. 5. Transition is measured ±500mV from steady state with C guaranteed but not 100% tested. SWITCHING WAVEFORMS (READ CYCLE) (1,2,4) READ CYCLE (1,3,4) READ CYCLE (1,4) READ CYCLE Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. IL. = 5pF as shown in Figure 1B. The parameter is L CS18LV10245 Rev. 1 ...

Page 9

... Data to Write Time Overlap DVWH Data Hold from Write Time WHDX End of Write to Output Active WHOX OW Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved 0~70 Description MIN MAX MIN MAX CS18LV10245 Vcc = 5.0V ) -55 - ...

Page 10

... High Speed Super Low Power SRAM 128K-Word By 8 Bit SWITCHING WAVEFORMS (WRITE CYCLE) Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. CS18LV10245 Rev. 1 ...

Page 11

... During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output remain in a high impedance state. Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. CS18LV10245 Rev. 1 ...

Page 12

... Transition is measured ±500mV from steady state with C The parameter is guaranteed but not 100% tested. 11 measured from the later of /CE going low to the end of write. CW Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved CS18LV10245 = 5pF as shown in Figure 1B. Rev. 1 ...

Page 13

... E: 32TSOP I (8x20mm) L: 32PDIP (600mil) 2. GREEN PACKAGE: CS18LV10245 Package: C: 32SOP (450mil) D: 32STSOP I (8x13.4mm) E: 32TSOP I (8x20mm) Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. Green Code A: Pb Free + Halogen Free (SOP / TSOP Types) CS18LV10245 Speed: 55: 55NS 70: 70ns Grade: C: 0~70°C I: -40~85° ...

Page 14

... Nom. 0.0433 0.004 0.039 0.009 0.008 0.465 Max. 0.0473 0.006 0.041 0.011 0.009 0.008 0.006 0.469 - CS18LV10245 b WITH PLATING c c1 BASE METAL b1 SECTION A 11.176 13.792 1.118 0.584 1.194 0° 11.303 14 ...

Page 15

... Min. 0.010 0.149 0.013 0.045 0.006 1.645 _ Nom. 0.154 0.018 0.050 0.010 1.650 _ Max. 0.159 0.023 0.055 0.014 1.655 CS18LV10245 Seating Plane y 12°(2x) GAUGE PLANE A SEATING PLANE A 12°(2x "A" DETAIL VIEW SECTION A ...

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