CS18LV10245 CHIPLUS, CS18LV10245 Datasheet - Page 12
CS18LV10245
Manufacturer Part Number
CS18LV10245
Description
HIgh Speed Super Low Power SRAM
Manufacturer
CHIPLUS
Datasheet
1.CS18LV10245.pdf
(15 pages)
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6. /OE is continuously low (/OE = V
7. D
8. D
9. If /CE is low during this period, DQ pins are in the output state. Then the data input
10. Transition is measured ±500mV from steady state with C
11. T
Copyright
signals of opposite phase to the outputs must not be applied to them.
The parameter is guaranteed but not 100% tested.
CW
OUT
OUT
is measured from the later of /CE going low to the end of write.
is the read data of next address.
is the same phase of write data of this write cycle.
2004 March Chiplus Semiconductor Corp. All rights reserved.
128K-Word By 8 Bit
High Speed Super Low Power SRAM
IL
).
L
= 5pF as shown in Figure 1B.
CS18LV10245
.
Rev. 1.2
P 12