CS18LV10245 CHIPLUS, CS18LV10245 Datasheet - Page 3

• Manufacturer Part Number: CS18LV10245
• Description: HIgh Speed Super Low Power SRAM
• Manufacturer: CHIPLUS

A0-A16
Address Input
/CE
Chip Enable Input
CE2
Chip Enable 2 Input
/WE
Write Enable Input
/OE
Output Enable Input
DQ0-DQ7
Data Input/Output
Ports
Vcc
Gnd
Copyright
Disabled
Selected
Output
PIN DESCRIPTIONS
TRUTH TABLE
MODE
Read
Write
Not
Name
2004 March Chiplus Semiconductor Corp. All rights reserved.
/WE
X
X
H
H
L
128K-Word By 8 Bit
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM.
/CE is active LOW and CE2 is active HIGH. Both chip enables must be active
when data read from or write to the device. If either chip enable is not active,
the device is deselected and is in a standby power mode. The DQ pins will be
in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins; when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the
RAM.
Power Supply
Ground
High Speed Super Low Power SRAM
/CE
H
X
L
L
L
CE2
H
H
H
X
L
/OE
H
X
X
X
L
Function
DQ0~7
High Z
High Z
D
D
OUT
IN
CS18LV10245
Vcc Current
I
CCSB
I
I
I
, I
CC
CC
CC
.
CCSB1
Rev. 1.2
P 3