CS18LV10245 CHIPLUS, CS18LV10245 Datasheet - Page 11

• Manufacturer Part Number: CS18LV10245
• Description: HIgh Speed Super Low Power SRAM
• Manufacturer: CHIPLUS

NOTES:
1. T
2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All
3. T
4. During this period, DQ pins are in the output state so that the input signals of opposite
5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the
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signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
of write cycle.
phase to the outputs must not be applied.
/WE transition, output remain in a high impedance state.
AS
WR
is measured from the address valid to the beginning of write.
is measured from the earlier of /CE or /WE going high or CE2 going low at the end
2004 March Chiplus Semiconductor Corp. All rights reserved.
128K-Word By 8 Bit
High Speed Super Low Power SRAM
CS18LV10245
.
Rev. 1.2
P 11