ST93C06C ST Microelectronics, ST93C06C Datasheet - Page 7

• Manufacturer Part Number: ST93C06C
• Description: 256 bit 16 x 16 or 32 x 8 SERIAL MICROWIRE EEPROM
• Manufacturer: ST Microelectronics

Figure 6. READ, WRITE, EWEN, EWDS Sequences
Notes: 1. An: n = 3 for x16 org. and 4 for x8 org.
If the ST93C06 is still performing the erase cycle,
the Busy signal (Q = 0) will be returned if S is driven
high, and the ST93C06 will ignore any data on the
bus. When the erase cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the ST93C06 is ready to receive a new instruction.
Write
The Write instruction (WRITE) is followed by the
address and the 8 or 16 data bits to be written. Data
input is sampled on the Low to High transition of
the clock. After the last data bit has been sampled,
Chip Select (S) must be brought Low before the
next rising edge of the clock (C) in order to start the
2. Xn: n = 3 for x16 org. and 4 for x8 org.
READ
WRITE
ERASE
WRITE
ENABLE
S
Q
S
Q
S
D
D
D
1 1 0
1 0
1
0
CODE
CODE
CODE
OP
1 X
OP
0
OP
X X
1
X
1
An A0
An
Xn X0
ADDR
ADDR
A0
Qn
Dn
DATA OUT
DATA IN
self-timed programming cycle. If the ST93C06 is
still performing the write cycle, the Busy signal (Q
= 0) will be returned if S is driven high, and the
ST93C06 will ignore any data on the bus. When the
write cycle is completed, the Ready signal (Q = 1)
will indicate (if S is driven high) that the ST93C06
is ready to receive a new instruction. Programming
is internally self-timed (the external clock signal on
C input may be disconnected or left running after
the start of a programming cycle) and does not
require an Erase instruction prior to the Write in-
struction (The Write instruction includes an auto-
matic erase cycle before programing data).
ERASE
WRITE
DISABLE
S
D
D0
Q0
BUSY
1
STATUS
CHECK
0
CODE
ST93C06, ST93C06C
0
OP
0
0
READY
Xn X0
AI00822D
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