ST93C46CM1 ST Microelectronics, ST93C46CM1 Datasheet - Page 5
ST93C46CM1
Manufacturer Part Number
ST93C46CM1
Description
1K 64 x 16 or 128 x 8 SERIAL MICROWIRE EEPROM
Manufacturer
ST Microelectronics
Datasheet
1.ST93C46CM1.pdf
(13 pages)
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Figure 5. Synchronous Timing, Read or Write
DESCRIPTION (cont’d)
counter automatically rolls over to ’00’ when the
highest address is reached.
Programming is internally self-timed (the external
clock signal on C input may be disconnected or left
running after the start of a Write cycle) and does
not require an erase cycle prior to the Write instruc-
tion. The Write instruction writes 8 or 16 bits at one
time into one of the 128 bytes or 64 words. After
the start of the programming cycle a Busy/Ready
signal is available on the Data output (Q) when
Chip Select (S) is High.
C
S
D
Q
C
S
D
Q
Hi-Z
An
tDVCH
Hi-Z
ADDRESS INPUT
An
tDVCH
ADDRESS/DATA INPUT
tCHQL
tCHDX
A0
tCHDX
A0/D0
An internal feature of the ST93C46 provides
Power-on Data Protection by inhibiting any opera-
tion when the Supply is too low. The design of the
ST93C46 and the High Endurance CMOS technol-
ogy used for its fabrication give an Erase/Write
cycle Endurance of 1,000,000 cycles and a data
retention of 40 years.
The DU (Don’t Use) pin does not affect the function
of the memory and it is reserved for use by SGS-
THOMSON during test sequences.The pin may be
left unconnected or may be connected to V
V
mended for the lowest standby power consump-
tion.
SS
. Direct connection of DU to V
tCHQV
tCLSL
ST93C46A/46C/46T, ST93C47C/47T
Q15/Q7
tSLSH
tSLCH
tSHQV
WRITE CYCLE
tW
DATA OUTPUT
BUSY
tSLQZ
READY
tSLQZ
AI01429
Q0
tCLSL
SS
AI00820C
tSLSH
is recom-
CC
5/13
or