74ACT2708PC Fairchild Semiconductor, 74ACT2708PC Datasheet

IC MEMORY FIRST OUT 64X9 28-DIP

74ACT2708PC

Manufacturer Part Number
74ACT2708PC
Description
IC MEMORY FIRST OUT 64X9 28-DIP
Manufacturer
Fairchild Semiconductor
Series
74ACTr
Datasheet

Specifications of 74ACT2708PC

Function
Asynchronous, Synchronous
Memory Size
576 (9 x 64)
Data Rate
60MHz
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Access Time
-
Other names
74ACT2708

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ACT2708PC
Manufacturer:
TI
Quantity:
658
© 1999 Fairchild Semiconductor Corporation
74ACT2708
64 x 9 First-In, First-Out Memory
General Description
The ACT2708 is an expandable first-in, first-out memory
organized as 64 words by 9 bits. An 85 MHz shift-in and 60
MHz shift-out typical data rate makes it ideal for high-speed
applications. It uses a dual port RAM architecture with
pointer logic to achieve the high speed with negligible fall-
through time.
Separate Shift-In (SI) and Shift-Out (SO) clocks control the
use of synchronous or asynchronous write or read. Other
controls include a Master Reset (MR) and Output Enable
(OE) for initializing the internal registers and allowing the
data outputs to be 3-STATE. Input Ready (IR) and Output
Ready (OR) signal when the FIFO is ready for I/O opera-
tions. The status flags HF and FULL indicate when the
FIFO is full, empty or half full.
The FIFO can be expanded to provide different word
lengths by tying off unused data inputs.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
FACT
Order Number
74ACT2708PC
is a trademark of Fairchild Semiconductor Corporation.
Pin Assignment for DIP
Package Number
N28B
28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide
DS010144.prf
Features
Applications
• High-speed disk or tape controllers
• A/D output buffers
• High-speed graphics pixel buffer
• Video time base correction
• Digital filtering
Pin Descriptions
64-words by 9-bit dual port RAM organization
85 MHz shift-in, 60 MHz shift-out data rate, typical
Expandable in word width only
TTL-compatible inputs
Asynchronous or synchronous operation
Asynchronous master reset
Outputs source/sink 8 mA
3-STATE outputs
Full ESD protection
Input and output pins directly in line for easy board lay-
out
TRW 1030 work-alike operation
Package Description
D
MR
OE
SI
SO
IR
OR
HF
FULL
O
0
0
Pin Names
–D
–O
8
8
Data Inputs
Master Reset
Output Enable Input
Shift-In
Shift-Out
Input Ready
Output Ready
Half Full Flag
Full Flag
Data Outputs
February 1989
Revised January 1999
Description
www.fairchildsemi.com

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74ACT2708PC Summary of contents

Page 1

... Ordering Code: Order Number Package Number 74ACT2708PC N28B 28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram ...

Page 2

Logic Symbol Block Diagram www.fairchildsemi.com 2 ...

Page 3

Functional Description INPUTS Data Inputs (D – Data inputs for 9-bit wide data are TTL-compatible. Word width can be reduced by trying unused inputs to ground and leaving the corresponding outputs open. Reset (MR) Reset is accomplished ...

Page 4

MODES OF OPERATION Mode 1: Shift in Sequence for FIFO Empty to Full Sequence of Operation 1. Input Ready is initially HIGH; HF and FULL flags are LOW. The FIFO is empty and prepared for valid data LOW ...

Page 5

Mode 2: Master Reset Sequence of Operation 1. Input and Output Ready, HF and FULL can be in any state before the reset sequence with Master Reset (MR) HIGH. 2. Master Reset goes LOW and clears the FIFO, setting up ...

Page 6

Mode 3: With FIFO Full, Shift-In is Held HIGH in Anticipation of an Empty Location Sequence of Operation 1. The FIFO is initially full and Shift-In goes HIGH initially HIGH. Shift-Out is LOW LOW. 2. Shift-Out ...

Page 7

Mode 4: Shift-Out Sequence, FIFO Full to Empty Sequence of Operation 1. FIFO is initially full and OR is HIGH, indicating valid data is at the output LOW goes HIGH, resulting in OR going LOW one ...

Page 8

Mode 5: With FIFO Empty, Shift-Out is Held HIGH in Anticipation of Data Sequence of Operation 1. FIFO is initially empty; Shift-Out goes HIGH. 2. Shift-In pulse loads data into the FIFO and IR falls. HF rises propagation delay t ...

Page 9

FIFO Expansion Word Width Expansion Word width can be increased by connecting the corresponding input control signals of multiple devices. Flags can be mon- itored to obtain a composite signal by ANDing the corresponding flags. Note: AND the corresponding flags ...

Page 10

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...

Page 11

AC Electrical Characteristics Symbol Parameter t Propagation Delay, t PLH Propagation Delay, t PHL Propagation Delay, t PLH IHF Propagation Delay, t PHL ...

Page 12

AC Electrical Characteristics Symbol Parameter t HF Pulse Width Pulse Width Pulse Width Fall-Through Times, t PLH Output Enable PZL OE ...

Page 13

Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL ...

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