AD9219BCPZRL-65 Analog Devices, Inc., AD9219BCPZRL-65 Datasheet - Page 21

• Manufacturer Part Number: AD9219BCPZRL-65
• Description: Quad, 10-bit, 40/65 Msps Serial Lvds 1.8 V A/d Converter
• Manufacturer: Analog Devices, Inc.

CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9219 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
Figure 50 shows one preferred method for clocking the AD9219.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9219 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9219 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure 51. The AD9510/AD9511/AD9512/AD9513/AD9514/
AD9515
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
CLOCK
INPUT
INPUT
INPUT
50 *
*50 RESISTORS ARE OPTIONAL
50 *
*50 RESISTORS ARE OPTIONAL
family of clock drivers offers excellent jitter performance.
Figure 50. Transformer Coupled Differential Clock
50
0.1µF
Figure 52. Differential LVDS Sample Clock
Figure 51. Differential PECL Sample Clock
0.1µF
0.1µF
50 *
50 *
0.1µF
0.1µF
100
ADT1–1WT, 1:1Z
MIN-CIRCUITS
CLK
PECL DRIVER
CLK
CLK
AD9510/1/2/3/4/5
LVDS DRIVER
CLK
AD9510/1/2/3/4/5
XFMR
0.1µF
240
0.1µF
0.1µF
SCHOTTKY
HSM2812
DIODES:
240
100
100
0.1µF
0.1µF
0.1µF
0.1µF
CLK+
CLK–
AD9219
CLK+
CLK–
CLK+
CLK–
AD9219
AD9219
ADC
ADC
ADC
Rev. 0 | Page 21 of 52
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 53). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9219 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9219. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. The DCS
function cannot be turned off.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 10 clock cycles
to allow the DLL to acquire and lock to the new rate.
CLOCK
CLOCK
INPUT
INPUT
*50 RESISTOR IS OPTIONAL
50 *
*50 RESISTOR IS OPTIONAL
50 *
Figure 53. Single-Ended 1.8 V CMOS Sample Clock
Figure 54. Single-Ended 3.3 V CMOS Sample Clock
0.1µF
0.1µF
0.1µF
0.1µF
CLK
CLK
CLK
CLK
AD9510/1/2/3/4/5
CMOS DRIVER
AD9510/1/2/3/4/5
CMOS DRIVER
0.1µF
OPTIONAL
OPTIONAL
100
100
39k
0.1µF
0.1µF
0.1µF
AD9219
CLK+
CLK–
CLK+
CLK–
AD9219
AD9219
ADC
ADC