AD9219BCPZRL-65 Analog Devices, Inc., AD9219BCPZRL-65 Datasheet - Page 27

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AD9219BCPZRL-65

Manufacturer Part Number
AD9219BCPZRL-65
Description
Quad, 10-bit, 40/65 Msps Serial Lvds 1.8 V A/d Converter
Manufacturer
Analog Devices, Inc.
Datasheet
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9219. This is gained up by a factor of 2 internally, setting
V
of 2 V p-p. The V
VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9219. The recommended capacitor values and
configurations for the AD9219 reference pin can be found in
Figure 64.
Table 12. Reference Settings
Selected
Mode
External
Internal,
REF
Reference
2 V p-p FSR
to 1.0 V, which results in a full-scale differential input span
90
85
80
75
70
65
60
55
600
500
400
300
200
100
2
0
2
4
SENSE
Voltage
AVDD
AGND to 0.2 V
4
REF
6
is set internally by default; however, the
Figure 63. IAVDD vs. RBIAS
Figure 62. SFDR vs. RBIAS
6
RESISTANCE (k )
8
RESISTANCE (k )
8
Resulting
VREF (V)
N/A
1.0
10
SFDR
10
12
SNR
12
14
16
16
Resulting
Differential
Span (V p-p)
2 × external
2.0
reference
18
70
65
60
55
50
45
40
35
18
Rev. 0 | Page 27 of 52
Internal Reference Operation
A comparator within the AD9219 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 64), setting VREF to 1 V.
The REFT and REFB pins establish their input span of the ADC
core from the reference configuration. The analog input full-
scale range of the ADC equals twice the voltage at the reference
pin for either an internal or an external reference configuration.
If the reference of the AD9219 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 66
depicts how the internal reference voltage is affected by loading.
1µF
1µF
+
SENSE
0.1µF
0.1µF
SENSE
R2
R1
V
VIN+
VIN–
V
VIN+
VIN–
REF
REF
Figure 64. Internal Reference Configuration
Figure 65. External Reference Operation
SELECT
LOGIC
SELECT
LOGIC
CORE
ADC
CORE
ADC
0.5V
0.5V
REFT
REFB
REFT
REFB
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
AD9219
+
+
2.2µF
2.2µF

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