74AUP1G74GM,125 NXP Semiconductors, 74AUP1G74GM,125 Datasheet
74AUP1G74GM,125
Specifications of 74AUP1G74GM,125
74AUP1G74GM-G
74AUP1G74GM-G
935281287125
Related parts for 74AUP1G74GM,125
74AUP1G74GM,125 Summary of contents
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Low-power D-type flip-flop with set and reset; positive-edge trigger Rev. 5 — 26 July 2010 1. General description The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74AUP1G74DC −40 °C to +125 °C 74AUP1G74GT −40 °C to +125 °C 74AUP1G74GF −40 °C to +125 °C 74AUP1G74GD −40 °C to +125 °C 74AUP1G74GM −40 °C to +125 °C 74AUP1G74GN − ...
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... NXP Semiconductors Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74AUP1G74 GND 001aae322 Fig 4. Pin configuration SOT765-1 74AUP1G74 Product data sheet Low-power D-type flip-flop with set and reset; positive-edge trigger Fig 5. All information provided in this document is subject to legal disclaimers. Rev. 5 — 26 July 2010 ...
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... NXP Semiconductors 74AUP1G74 GND 4 Transparent top view Fig 6. Pin configuration SOT996-2 6.2 Pin description Table 3. Pin description Symbol Pin SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 GND Functional description Table 4. Function table for asynchronous operation Input [ HIGH voltage level LOW voltage level don’t care. ...
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... NXP Semiconductors Table 5. Function table for synchronous operation Input [ HIGH voltage level LOW voltage level don’t care; ↑ = LOW-to-HIGH CP transition state after the next LOW-to-HIGH CP transition. n+1 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 25 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF Δ ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF Δ ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +125 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF Δ ...
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... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation see pd delay see see maximum CP; see max frequency 74AUP1G74 Product data sheet Low-power D-type flip-flop with set and reset; positive-edge trigger ...
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... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation see pd delay see see maximum CP; see max frequency 74AUP1G74 Product data sheet Low-power D-type flip-flop with set and reset; positive-edge trigger …continued ...
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... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation see pd delay see see maximum CP; see max frequency 74AUP1G74 Product data sheet Low-power D-type flip-flop with set and reset; positive-edge trigger …continued ...
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... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation see pd delay see see maximum CP; see max frequency 74AUP1G74 Product data sheet Low-power D-type flip-flop with set and reset; positive-edge trigger …continued ...
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... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions pF and set-up time HIGH; su see LOW; see hold time D to CP; see recovery time RD; see rec SD; see 74AUP1G74 Product data sheet Low-power D-type flip-flop with set and reset; positive-edge trigger … ...
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... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t pulse width CP HIGH or LOW; W see LOW; see power MHz dissipation V = GND capacitance [1] All typical values are measured at nominal V [ the same as t and PLH ...
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... NXP Semiconductors 12. Waveforms CP input D input Q output Q output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical output voltage levels that occur with the output load Fig 8. The clock input (CP) to output (Q, Q) propagation delays, the data input (D) to clock input (CP) set-up and hold times and the clock input (CP) pulse width and maximum frequency Table 10 ...
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... NXP Semiconductors CP input SD input RD input Q output Q output Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 9. The set input (SD) and reset input (RD) to output (Q, Q) propagation delays, the set input (SD) and reset ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 10. Test circuit for measuring switching times Table 11. ...
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... NXP Semiconductors 13. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 14. Package outline SOT996-2 (XSON8U) ...
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... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 13. Revision history Document ID Release date 74AUP1G74 v.5 20100726 • Modifications: Added type number 74AUP1G74GF (SOT1089/XSON8 package). ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74AUP1G74 Product data sheet Low-power D-type flip-flop with set and reset ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 13 Package outline ...