MCM69F819 Motorola, MCM69F819 Datasheet
MCM69F819
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MCM69F819 Summary of contents
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... Bit Flow–Through BurstRAM Synchronous Fast Static RAM The MCM69F819 bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC high performance microprocessors organized as 256K words of 18 bits each. This device integrates input registers, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications ...
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... LBO ADV K ADSC ADSP SA SA1 SA0 SGW SW SBa SBb SE1 SE2 SE3 G MCM69F819 2 FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 18 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER b K2 ENABLE REGISTER 2 18 256K x 18 ARRAY DATA–IN REGISTER K DQa – DQb ...
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... DQa 74 73 DQa 72 DQa DDQ 69 DQa 68 DQa DQa 63 DQa DDQ DQa 58 DQa DDQ 4546 Not to Scale MCM69F819 3 ...
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... MCM69F819 4 Symbol Type ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address ...
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... Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low Supply Core Power Supply. V DDQ Supply I/O Power Supply Supply Ground. NC — No Connection: There is no connection to the chip. Description MCM69F819 5 ...
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... INTERLEAVED BURST ADDRESS TABLE 1st Address (External) 2nd Address (Internal X00 X01 X10 X11 WRITE TRUTH TABLE Cycle Type Read Read Write Byte a Write Byte b Write All Bytes Write All Bytes MCM69F819 6 SE2 SE3 ADSP ADSC ADV ...
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... Symbol Single Layer Board Four Layer Board Symbol Single Layer Board Four Layer Board This device contains circuitry to protect the Max Unit Notes C C C/W 4 Max Unit Notes C C C/W 4 MCM69F819 7 ...
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... Input High Voltage Input High Voltage (I/O Pins) RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O Supply Parameter Supply Voltage I/O Supply Voltage Input Low Voltage Input High Voltage Input High Voltage (I/O Pins – 1.0 V MCM69F819 8 (Voltages Referenced Symbol DDQ IH2 (Voltages Referenced ...
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... MCM69F819–7.5 I DDA — MCM69F819–8 MCM69F819–8.5 MCM69F819–11 I SB2 — I SB3 — MCM69F819–7.5 I SB4 — MCM69F819–8 MCM69F819–8.5 MCM69F819–11 I SB5 — — 1.7 V OL2 — V OH2 2.4 V DDQ – 0.2 V. CMOS levels for other inputs are ...
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... 1.25 V Figure 2. AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V See Figure 2 Unless Otherwise Noted MCM69F819–11 50 MHz Max Min Max U i Unit Notes N — 20 — ns — 4.5 — ns — 4.5 — ns 8.5 — 3.5 — 3.5 ns — 0 — ...
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... Fall time is measured from 2.0 to 0.5 V unloaded. Figure 4. Unloaded Rise and Fall Time Characterization MOTOROLA FAST SRAM LUMPED CAPACITANCE (pF) OUTPUT LOAD OUTPUT TEST POINT BUFFER UNLOADED RISE AND FALL TIME MEASUREMENT 2.0 2.0 0.5 2.0 0 100 0.5 2.0 0 MCM69F819 11 ...
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... PULL–DOWN VOLTAGE (V) I (mA) MIN I (mA) MAX – 0 0.4 10 0.8 20 1.25 31 1.6 40 2.8 40 3.2 40 3.4 40 Figure 5. Typical Output Buffer Characteristics MCM69F819 12 2.9 2.5 2.3 2.1 – 105 – 105 – 105 1.25 – 83 – 70 0.8 – 30 – (a) Pull–Up for 2.5 V I/O Supply 3.6 3.135 2.8 – 150 – 150 1.65 – 150 – ...
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... MOTOROLA FAST SRAM MCM69F819 13 ...
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... BURST READ) NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state ( Best results are obtained < 0.2 V. MCM69F819 14 APPLICATION INFORMATION operation for all three stop clock modes, stop read, stop write, and stop deselect: ...
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... For lowest power operation, all data and address lines should be held in a low ( state and control lines held in an inactive state. MOTOROLA FAST SRAM STOP CLOCK WITH WRITE TIMING D( FIXED (SEE NOTE) HIGH–Z CLOCK STOP (CONTINUE BURST WRITE) A2 D(A2) WAKE UP ADSC (INITIATES BURST WRITE) MCM69F819 15 ...
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... NOTE: While the clock is stopped, DATA IN must be fixed in a high ( low ( state to reduce the DC current of the input buffers. For lowest power operation, all data and address lines should be held in a low ( state and control lines held in an inactive state. MCM69F819 FIXED (SEE NOTE) HIGH– ...
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... SRAMs can be used in other high speed L2 cache or memory applications that do not require the burst address feature. Most L2 caches designed with a synchronous inter- face can make use of the MCM69F819. The burst counter feature of the BurstRAM can be disabled, and the SRAM can be configured to act upon a continuous stream of addresses. ...
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... TOP VIEW SIDE VIEW A1 MCM69F819 18 PACKAGE DIMENSIONS ZP PACKAGE BUMP PBGA CASE 999–02 b 119X 0 0. 16X BOTTOM VIEW 0.25 A 0.35 A 0.20 A SEATING ...
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... REF S 0.20 ––– 0.008 ––– R1 0.08 ––– 0.003 ––– R2 0.08 0.20 0.003 0.008 ––– 0 ––– MCM69F819 19 ...
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... Motorola, Inc. Motorola, Inc Equal Mfax is a trademark of Motorola, Inc. JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, CUSTOMER FOCUS CENTER: 1-800-521-6274 MOTOROLA FAST SRAM MCM69F819/D ...