MCM69F819 Motorola, MCM69F819 Datasheet - Page 5
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MCM69F819
Manufacturer Part Number
MCM69F819
Description
256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
Manufacturer
Motorola
Datasheet
1.MCM69F819.pdf
(20 pages)
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MOTOROLA FAST SRAM
TQFP PIN DESCRIPTIONS
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50,
39, 42, 43, 51, 52, 53, 56, 57, 64, 66, 75,
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38,
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24
4, 11, 20, 27, 54, 61, 70, 77
55, 60, 67, 71, 76, 90
5, 10, 17, 21, 26, 40,
80, 81, 82, 99, 100
Pin Locations
15, 41, 65, 91
78, 79, 95, 96
(a) (b)
36, 37
93, 94
85
84
83
86
89
31
88
98
97
92
87
SA1, SA0
Symbol
V DDQ
ADSC
ADSP
SGW
ADV
V DD
DQx
LBO
V SS
SBx
SE1
SE2
SE3
SW
NC
SA
G
K
Supply
Supply
Supply
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
—
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b). SGW overrides SBx.
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
Core Power Supply.
I/O Power Supply.
Ground.
No Connection: There is no connection to the chip.
Description
MCM69F819
5