MCM69F819 Motorola, MCM69F819 Datasheet - Page 14

• Manufacturer Part Number: MCM69F819
• Description: 256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
• Manufacturer: Motorola

MCM69F819
14
STOP CLOCK OPERATION
state and data values even though the clock is not running
(full static operation). The SRAM design allows the clock to
start with ADSP and ADSC, and stops the clock after the last
write data is latched, or the last read data is driven out.
and parametrics must be strictly maintained. For example,
clock pulse width and edge rates must be guaranteed when
starting and stopping the clocks.To achieve the lowest power
In the stop clock mode of operation, the SRAM will hold all
When starting and stopping the clock, the AC clock timing
ADDRESS
NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (V IL ).
ADSP
ADV
DQx
K
Best results are obtained if V IL < 0.2 V.
BURST READ)
(INITIATES
ADSP
A1
BURST READ)
CLOCK STOP
(CONTINUE
STOP CLOCK WITH READ TIMING
Q(A1)
APPLICATION INFORMATION
operation for all three stop clock modes, stop read, stop
write, and stop deselect:
clock modes, stop read, stop write, and stop deselect:
Q(A1 + 1)
To achieve the lowest power operation for all three stop
Force the clock to a low state.
Force the control signals to an inactive state (this
guarantees any potential source of noise on the clock
input will not start an unplanned on activity).
Force the address inputs to a low state (V IL ), preferably
< 0.2 V.
(INITIATES BURST READ)
WAKE UP ADSP
A2
MOTOROLA FAST SRAM
Q(A2)