LTC3589 Linear Technology, LTC3589 Datasheet - Page 32

• Manufacturer Part Number: LTC3589
• Description: 8-Output Regulator
• Manufacturer: Linear Technology

OPERATION
LTC3589
Figure 16 shows the timing of the IRQ and IRQSTAT
status register following a warning (V
temperature warning) event. When a warning occurs, IRQ
is latched LOW and bit IRQSTAT[4] or IRQSTAT[5] is set.
IRQ remains LOW until I
written. The status bits in the IRQSTAT register will remain
active until CLIRQ is accessed and the warning condition
has passed.
Figure 17 shows the timing of the IRQ pin and IRQSTAT
status register following a fault induced hard shutdown
event. When a fault occurs, IRQ is latched LOW and bit
IRQSTAT[3], IRQSTAT[5], or IRQSTAT[7] is set. IRQ re-
mains LOW until I
When the CLIRQ command has been issued, the IRQSTAT
status bit remains set for the one second enable inhibit
time or as long as the fault condition persists, whichever
is longer.
32
Figure 16. IRQ and IRQSTAT Status Register Warning Timing
Figure 17. IRQ and IRQSTAT Status Register Fault Timing
TSD OR UV
OR PGOOD FAULT
WARNING
IRQSTAT
CLIRQ
IRQ
IRQSTAT
TSD, UV,
CLIRQ
2
IRQ
C command register CLIRQ is accessed.
2
1 SEC
C command register CLIRQ is
IN
1 SEC
3589 F16
<2.9V or high
3589 F17
Fault Induced Shutdown
Any of the three fault conditions will initiate a hard reset
shutdown triggering the following events: 1) A bit corre-
sponding to the fault is set in status register IRQSTAT, 2)
IRQ and WAKE pins are pulled LOW, 3) enable pin inputs
are ignored and the regulators are disabled, 4) all enable
bits and software control mode bit in the output voltage
enable OVEN command register are cleared, and 5) the
pushbutton controller is sent to the PDN state for one
second and then to POFF . Re-enabling of regulators is
inhibited until both the fault condition and the one second
time out have passed to allow regulator outputs suffi cient
time to discharge. When one second timeout and the fault
condition are both passed, if PWR_ON is HIGH, WAKE will
come up and the LTC3589 will respond to any enable pins
that are also HIGH.
I
I
The LTC3589 communicates with a bus master using the
standard I
SCL, must be HIGH when the bus is not in use. External
pull-up resistors or current sources, such as the LTC1694
SMBus accelerator, are required on these lines. The
LTC3589 is both a slave receiver and slave transmitter. The
I
the DV
power supply as the bus pull-up resistors.
The I
pin. When DV
port is reset to power-on states and registers are set to
default values.
2
2
2
C OPERATION
C Interface
C control signals, SDA and SCL are scaled internally to
2
C port has an under voltage lockout on the DV
DD
supply. DV
2
C 2-wire interface. The two bus lines, SDA and
DD
is below approximately 1V, the I
DD
should be connected to the same
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2
C serial
3589p
DD