LTC3589 Linear Technology, LTC3589 Datasheet - Page 35

• Manufacturer Part Number: LTC3589
• Description: 8-Output Regulator
• Manufacturer: Linear Technology

OPERATION
I
Table 16 and Table 17 show the LTC3589 I
and status registers. System control register (SCR1) sets
the operating modes of the switching regulators. Each
step-down switching regulator has pulse-skipping, Burst
Mode operation, or forced continuous operation. The
buck-boost switching regulator can be put in continuous
or Burst Mode operation.
The output voltage enable (OVEN) command register
controls the individual enables of each regulator. When
OVEN[7] is set to a logic LOW value, bits OVEN[6-0} are
ORed with their respective enable pins. When OVEN[7]
is HIGH, the input pins EN1, EN2, EN3, EN4, EN_LDO2,
and EN_LDO34, are ignored and the LTC3589 regulators
respond only to the OVEN register. When the regulators
are confi gured in a hard wired power-up sequence, setting
OVEN[7] allows software control of individual regulators.
When the PWR_ON pin is pulled LOW all bits in the OVEN
register are reset to POR state of 0x00.
System control register 2 (SCR2) controls the operation of
the regulator start-up and regulator power-good (PGOOD)
hard shutdown operation. Set command register SCR2[7]
to inhibit a hard shutdown of the regulators in the event
of an extended low output rail voltage. The low output
voltage event is still reported via the IRQ pin and IRQSTAT
status register. Set the bits in SCR2[6-0] LOW to force a
regulator to ignore its enable until its output has fallen to
less than 300mV (typical). If set HIGH, the regulator will
enable without waiting for its output to discharge and will
not engage the 2k discharge resistor.
LDO2 and step-down switching regulators 1 to 3 each have
a pair of control bits in the voltage change control register
VCCR. The reference select bit selects which of two 5-bit
words are used as inputs to the regulators feedback refer-
ence DAC inputs. The slew go bit initiates a DAC slew to
the voltage selected by the reference select bit. When the
slew is complete, the slew go bits are reset LOW.
Accessing the CLIRQ command register will clear the IRQ
pin and will let the IRQ pin to release HIGH. The pin is
2
C Command and Status Registers
2
C command
cleared when the LTC3589 acknowledges the sub-address.
Data written to the CLIRQ command register is ignored.
There are eight command registers that are used to store
the 5-bit dynamic target voltage input to the feedback
reference slewing DACs – B1DTV1, B1DTV2, B2DTV1,
B2DTV2, B3DTV1, B3DTV2, L2DTV1 and L2DTV2. The
registers ending with V2 use bits 4 through 0 to store
the V2 feedback reference voltage for the regulators. The
regulators input reference voltage is set to V2 by setting
the reference select bits HIGH in VCCR and writing to the
go bits in VCCR. The V2 voltage is also selected whenever
the VSTB pin is driven HIGH. The registers ending with
V1 use bits 4 through 0 to store the V1 feedback voltage
reference for the regulators. The regulators input refer-
ence voltage is set to V1 voltage by setting the reference
select bits LOW in command register VCCR. Whenever
a new dynamic target voltage is set, either by changing
the 5-bit value or by changing the reference select bits in
VCCR, the go bits in VCCR must be written to initiate the
dynamic voltage slew. When bit 5 in B1DTV1, B2DTV1,
B3DTV1, and L2DTV1 is LOW the PGOOD pin pulls LOW
during a dynamic voltage slew. Bits 7 and 6 in B1DTV1
set the switch DV/DT rate for all the step-down switch-
ing regulators. Bit 5 in registers B1DTV2, B2DTV2 and
B3DTV2 selects the switching frequency of step-down
switching regulators 1, 2 and 3. Writing the bit LOW sets
the switching frequency to 2.25MHz. Writing the bit HIGH
sets the switching frequency to 1.125MHz.
The dynamic slew rates of the four feedback reference
DACs are independently set using bits in voltage ramp rate
command register (VRRCR). The rate shown is the slew of
the DAC output as it slews up or down to its target value.
The slew rate of the output voltage is scaled by the gain of
the resistor divider network that sets the regulator output
voltage. For example, a regulator set to an output voltage
of 1.2V when the dynamic target voltage reference is 0.75V
has a gain of 1.6. Slewing the regulator output from 1.2V
to 1V requires slewing the DAC output down 125mV from
750mV to 625mV. With a VRRCR slew rate setting of 01
the slew time of the regulator output is 71μs.
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LTC3589
35
3589p