LTC4215 Linear Technology, LTC4215 Datasheet - Page 10

• Manufacturer Part Number: LTC4215
• Description: Hot Swap Controller
• Manufacturer: Linear Technology

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TI I G DIAGRA
LTC4215
The LTC4215 is designed to turn a board’s supply voltage
on and off in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. During
normal operation, the charge pump and gate driver turn
on an external N-channel MOSFET’s gate to pass power
to the load. The gate driver uses a charge pump that
derives its power from the V
gate driver is an internal 6.5V GATE-to-SOURCE clamp.
During start-up the inrush current is tightly controlled by
using current limit foldback, soft start dI/dt limiting and
output dV/dt limiting.
The current sense (CS) amplifi er monitors the load current
using the difference between the SENSE
and SENSE
rent in the load by pulling back on the GATE-to-SOURCE
voltage in an active control loop when the sense voltage
exceeds the commanded value. The CS amplifi er requires
20µA input bias current from both the SENSE
SENSE
A short circuit on the output to ground results in excessive
power dissipation during active current limiting. To limit
this power, the CS amplifi er regulates the voltage between
the SENSE
If an overcurrent condition persists, the internal circuit
breaker (CB) registers a fault when the sense voltage ex-
ceeds 25mV for more than 20µs. This indicates to the logic
that it is time to turn off the GATE to prevent overheating.
At this point the start-up TIMER pin voltage ramps down
using the 2µA current source until the voltage drops below
0.2V (comparator TM1) which tells the logic that the pass
transistor has cooled and it is safe to turn it on again if
OPERATIO
10
W
U
–
pins.
+
–
and SENSE
SDAI/SDAO
pin voltages. The CS amplifi er limits the cur-
t
HD, STA
SCL
U
CONDITION
START
–
pins at 75mV.
W
DD
pin. Also included in the
t
SU, DAT
+
(V
DD
t
t
HD, DATO,
HD, DATI
for SSOP)
+
and the
REPEATED START
CONDITION
overcurrent auto-retry is enabled. If the TIMER pin is tied
to INTV
an internal system timer in the logic.
The output voltage is monitored using the FB pin and the
Power Good (PG) comparator to determine if the power
is available for the load. The power good condition can be
signaled by the GPIO pin using an open-drain pulldown
transistor. The GPIO pin may also be confi gured to signal
power bad, or as a general purpose input (GP comparator),
or a general purpose open drain output.
The Functional Diagram shows the monitoring blocks of
the LTC4215. The group of comparators on the left side
includes the undervoltage (UV), overvoltage (OV), reset
(RST), enable ( ⎯ E ⎯ N ) and signal on (ON) comparators. These
comparators determine if the external conditions are valid
prior to turning on the GATE. But fi rst the two undervoltage
lockout circuits, UVLO1 and UVLO2, validate the input
supply and the internally generated 3.1V supply, INTV
UVLO2 also generates the power-up initialization to the
logic circuits as INTV
fi xed internal overvoltage comparator, OV2, detects that
V
an overvoltage fault and turns the GATE off.
Included in the LTC4215 is an 8-bit A/D converter. The con-
verter has a 3-input multiplexer to select between the ADIN
pin, the SOURCE pin and the V
An I
also allows the host to poll the device and determine if
faults have occurred. If the ⎯ A ⎯ L ⎯ E ⎯ R ⎯ T line is confi gured as an
interrupt, the host is enabled to respond to faults in real
time. The typical SDA line is divided into an SDAI (input)
DD
t
SU, STA
2
is greater than 15.6V, the part immediately generates
C interface is provided to read the A/D registers. It
CC
t
HD, STA
, the cool-down time defaults to 5 seconds on
t
SP
t
SP
t
SU, STO
CC
crosses this rising threshold. If the
CONDITION
STOP
DD
t
BUF
– SENSE voltage.
CONDITION
START
4215 TD01
4215fb
CC
.