LTC4215 Linear Technology, LTC4215 Datasheet - Page 18

• Manufacturer Part Number: LTC4215
• Description: Hot Swap Controller
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
LTC4215
same seven bit address with the R/ ⎯ W bit now set to one.
The LTC4215 acknowledges and send the contents of the
requested register. The transmission is ended when the
master sends a STOP condition. If the master acknowledges
the transmitted data byte, as in a Read Word command,
Figure 10, the LTC4215 repeats the requested register as
the second data byte.
Alert Response Protocol
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in the
ALERT register B is also set. If an alert is enabled, the cor-
18
U
U
S
ADDRESS
S
S
1 0 a4:a0
Figure 11. LTC4215 Serial Bus SDA Alert Response Protocol
Figure 8. LTC4215 Serial Bus SDA Write Word Protocol
Figure 10. LTC4215 Serial Bus SDA Read Word Protocol
Figure 9. LTC4215 Serial Bus SDA Read Byte Protocol
Figure 7. LTC4215 Serial Bus SDA Write Byte Protocol
ADDRESS
ADDRESS
1 0 a4:a0
W
1 0 a4:a0
S
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
ADDRESS
W
1 0 a4:a0
0
A
0
W
W
0
0
X X X X X b2:b0
A
0
A
0
S
COMMAND
U
0 0 0 1 1 0 0
RESPONSE
W
X X X X X b2:b0
X X X X X b2:b0
0
ADDRESS
COMMAND
COMMAND
ALERT
A
0
X X X X X b2:b0
COMMAND
R
1
A
0
A
0
S
A
0
A
0
1 0 a4:a0 0
responding fault causes the ⎯ A ⎯ L ⎯ E ⎯ R ⎯ T pin to pull low. After
the bus master controller broadcasts the Alert Response
Address, the LTC4215 responds with its address on the
SDA line and then release ⎯ A ⎯ L ⎯ E ⎯ R ⎯ T as shown in Figure 11.
The ⎯ A ⎯ L ⎯ E ⎯ R ⎯ T line is also released if the device is addressed
by the bus master. The ⎯ A ⎯ L ⎯ E ⎯ R ⎯ T signal is not pulled low
again until the FAULT register indicates a different fault
has occurred or the original fault is cleared and it occurs
again. Note that this means repeated or continuing faults
do not generate alerts until the associated FAULT register
bit has been cleared.
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
ADDRESS
ADDRESS
S
1 0 a4:a0
b7:b0
DATA
DEVICE
ADDRESS
A
0
1 0 a4:a0
b7:b0
DATA
A
0
R A
1 0
A P
1
4215 F11
X X X X X X X X
4215 F07
A P
0
R A
1 0
DATA
b7:b0
DATA
b7:b0 1
DATA
A
0
DATA
b7:b0
A P
0
A P
4215 F08
4215 F10
A P
1
4215 F11
4215fb