LTC4215 Linear Technology, LTC4215 Datasheet - Page 11

• Manufacturer Part Number: LTC4215
• Description: Hot Swap Controller
• Manufacturer: Linear Technology

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OPERATIO
APPLICATIO S I FOR ATIO
and SDAO (output). This simplifi es applications using an
optoisolator driven directly from the SDAO output. An
application which uses optoisolation is shown in Figure
14. The I
A typical LTC4215 application is in a high availability system
in which a positive voltage supply is distributed to power
individual cards. The device measures card voltages and
currents and records past and present fault conditions.
The system queries each LTC4215 over the I
and reads status and measurement information.
A basic LTC4215 application circuit is shown in Figure 1.
The following sections cover turn-on, turn-off and various
faults that the LTC4215 detects and acts upon. External
component selection is discussed in detail in the Design
Example section.
Turn-On Sequence
The power supply on a board is controlled by using an
external N-channel pass transistor (Q1) placed in the power
path. Note that resistor R
sistors R1, R2 and R3 defi ne undervoltage and overvoltage
levels. R5 prevents high frequency oscillations in Q1 and
R6 and C1 form an optional network that may be used to
provide an output dV/dt limited start-up.
2
C device address is decoded using the ADR0,
ALERT
GND
SDA
12V
SCL
V
IN
BACKPLANE
U
U
S
PLUG-IN
U
provides current detection. Re-
CARD
0.1µF
C
F
W
Z1
SA14A
2
R1
34k
1%
R2
1.02k
1%
R3
3.4k
1%
C periodically
Figure 1. Typical Application
U
OV
ON
SDAI
SDAO
SCL
ALERT
UV
C
0.68µF
TIMER
V
DD
SENSE
TIMER
ADR1 and ADR2 pins. These inputs have three states each
that decode into a total of 27 device addresses. ADR1 and
ADR2 are not available in the SSOP package; therefore,
those pins are NC in the address map.
Several conditions must be present before the external
MOSFET turns on. First the external supply, V
exceed its 2.84V undervoltage lockout level. Next the
internally generated supply, INTV
undervoltage threshold. This generates a 60µs to 120µs
power-on-reset pulse. During reset the fault registers are
cleared and the control registers are set or cleared as
described in the register section.
After a power-on-reset pulse, the LTC4215 goes through
the following turn-on sequence. First the UV and OV pins
indicate that input power is within the acceptable range,
which is indicated by bits C0-C1 in Table 4. Second, the EN
pin is externally pulled low. Finally, all of these conditions
must be satisfi ed for the duration of 100ms to ensure that
any contact bounce during insertion has ended.
When these initial conditions are satisfi ed, the ON pin is
checked and it’s state written to bit A3 in Table 2. If it is
high, the external MOSFET is turned on. If the ON pin is
low, the external MOSFET is turned on when the ON pin
0.005Ω
+
R
INTV
LTC4215UFD
S
SENSE
CC
C3
0.1µF
10Ω
ADR0
FDC653N
–
R5
GATE
Q1
ADR1
6.8nF
15k
NC
R6
C1
ADR2
SOURCE
GND
ADIN
GPIO
EN
SS
FB
4215 TA01a
R7
30.1k
1%
R8
3.57k
1%
C
7.5nF
SS
CC
, must cross its 2.64V
R4
24k
+
LTC4215
C
330µF
L
V
12V
OUT
DD
11
, must
4215fb