LTC6603 Linear Technology, LTC6603 Datasheet - Page 23

• Manufacturer Part Number: LTC6603
• Description: Dual Adjustable Lowpass Filter
• Manufacturer: Linear Technology

TYPICAL APPLICATIONS
PACKAGE DESCRIPTION
4.50 ± 0.05
DIODES INC
DMN2004DWK
CLK1
0
0
1
1
R
R
R
f
R1 = R
CLK
BIAS1
BIAS
BIAS
in MHz
GAIN1
GAIN0
=
IN k
CLK1
CLK0
LPF1
LPF0
BIAS1
> R
3.10 ± 0.05
2472
f
CLK
BIAS2
CLK0
0
1
0
1
R2 =
OR R
R
R
2.45 ± 0.05
BIAS1
(4 SIDES)
BIAS1
BIAS3
R3
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R
R
R
R
– R
• R
BIAS1
BIAS2
BIAS3
BIAS4
LTC6603 Parallel Clock Control
BIAS2
BIAS2
R2
f
f
f
f
DESIGN PROCEDURE
1. CHOOSE f
2. CALCULATE R
3. CALCULATE R2, R3 AND R
R3 =
CLK1
CLK2
CLK3
CLK4
V
OCM
R1
R
R
BIAS1
BIAS1
CLK1
0.1μF
0.1μF
– R
• R
BIAS1
, f
BIAS3
BIAS3
CLK2
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
, R
24
23
20
22
21
14
25
7
8
4
3
AND f
BIAS2
R
+INA
–INA
+INB
–INB
R
V
CAP
GAIN1
GAIN0(D0)
GND
GND
BIAS4
OCM
BIAS
1
V+
BIAS4
CLK3
AND R
IN
0.50 BSC
=
0.25 ±0.05
R1 • (R2 + R3) + R2 • R3
LTC6603
0.70 ±0.05
BIAS3
V+
2
A
PACKAGE
OUTLINE
LPF0(SCLK)
R1 • R2 • R3
CLKCNTL
LPF1(CS)
16
V+
+OUTB
–OUTB
+OUTA
–OUTA
24-Lead Plastic QFN (4mm × 4mm)
3V
CLKIO
D
SDO
SER
SDI
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
(Reference LTC DWG # 05-08-1697)
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
ON THE TOP AND BOTTOM OF PACKAGE
19
18
13
12
15
17
5
11
10
9
6
6603 TA02
PIN 1
TOP MARK
(NOTE 6)
3V
0.1
4.00 ± 0.10
UF Package
(4 SIDES)
DAC V
(USING THE LTC2630 INTERNAL REFERENCE)
IF R1 = 51.1k and R2 = 78.7k THEN
THE f
R1 =
CLK
1.137f
OUT
1
2
3
CS
SCLK
SDI
RANGE IS 12.36MHz to 80MHz
5.282 • 10
RANGE 0V TO 2.5V
8-BIT DAC
CLKHI
LTC2630
+ f
0.75 ± 0.05
V
GND
12
CLKLO
OUT
V+
6
5
4
, R2 =
3V
V
C
2.45 ± 0.10
(4-SIDES)
0.1μF
f
R2
CLKHI
0.200 REF
0.00 – 0.05
5.282 • 10
LTC6603 SPI Clock Control
– f
V
CLKLO
B
12
R1
R = 0.115
BOTTOM VIEW—EXPOSED PAD
V
IF V
IF V
f
0.1μF
0.1μF
CLK
C
RANGE 0V to 2.5V, V
TYP
C
C
= 2.472 • 10
= 0V THEN f
= 2.5V THEN f
24
23
20
22
21
14
25
7
8
4
3
www.DataSheet4U.com
CS1
+INA
–INA
+INB
–INB
R
V
CAP
GAIN1
GAIN0(D0)
GND
GND
OCM
BIAS
1
V+
12
CLK
23
IN
CLK
R1+ R2
R1• R2
= f
SCK
24
= f
LTC6603
B
CLKHI
V+
2
= 1.17V
CLKLO
LTC6603
A
0.50 BSC
LPF0(SCLK)
V
0.25 ± 0.05
SDI
B
CLKCNTL
LPF1(CS)
V
16
1
2
(UF24) QFN 0105
• R2
C
0.40 ± 0.10
V+
+OUTB
–OUTB
+OUTA
–OUTA
3V
CLKIO
D
SDO
SER
SDI
CS2
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
19
18
13
12
15
17
5
11
10
9
6
23
3V
6603 TA03
6603f
0.1μF