LTC690 Linear Technology, LTC690 Datasheet

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LTC690

Manufacturer Part Number
LTC690
Description
Microprocessor Supervisory Circuits
Manufacturer
Linear Technology
Datasheet

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FEATURES
APPLICATIO S
TYPICAL APPLICATIO
V
UL Recognized
Guaranteed Reset Assertion at V
1.5mA Maximum Supply Current
Fast (35ns Max) Onboard Gating of RAM Chip
Enable Signals
SO-8 and S16 Packaging
4.65V Precision Voltage Monitor
Power OK/Reset Time Delay: 50ms, 200ms
or Adjustable
Minimum External Component Count
1 A Maximum Standby Current
Voltage Monitor for Power-Fail
or Low-Battery Warning
Thermal Limiting
Performance Specified Over Temperature
Superior Upgrade for MAX690 Family
Critical P Power Monitoring
Intelligent Instruments
Battery-Powered Computers and Controllers
Automotive Systems
IN
10 F
10k
51k
7.5V
MICROPROCESSOR RESET, BATTERY BACK-UP, POWER FAILURE
WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR MICROPROCESSOR SYSTEMS
+
V
IN
LT
®
ADJ
1086-5
®
V
U
OUT
+
5V
File # E145770
100 F
U
CC
0.1 F
3V
= 1V
V
V
PFI
LTC690/LTC691
LTC694/LTC695
CC
BATT
GND
RESET
V
WDI
PFO
OUT
0.1 F
0.1 F
100
DESCRIPTIO
The LTC
monitoring and battery control functions for microproces-
sor reset, battery back-up, CMOS RAM write protection,
power failure warning and watchdog timing. A precise
internal voltage reference and comparator circuit monitor
the power supply line. When an out-of-tolerance condition
occurs, the reset outputs are forced to active states and the
chip enable output unconditionally write-protects external
memory. In addition, the RESET output is guaranteed to
remain logic low even with V
The LTC690 family powers the active CMOS RAMs with a
charge pumped NMOS power switch to achieve low drop-
out and low supply current. When primary power is lost,
auxiliary power, connected to the battery input pin, powers
the RAMs in standby through an efficient PMOS switch.
For an early warning of impending power failure, the
LTC690 family provides an internal comparator with a
user-defined threshold. An internal watchdog timer is also
available, which forces the reset pins to active states when
the watchdog input is not toggled prior to a preset time-out
period.
POWER TO
CMOS RAM
I/O LINE
P RESET
P NMI
, LTC and LT are registered trademarks of Linear Technology Corporation.
SYSTEM
P
®
POWER
690 family provides complete power supply
690 TA01
P
Supervisory Circuits
U
Microprocessor
5
4
1
3
2
0
0
LTC694/LTC695
LTC690/LTC691
CC
T
EXTERNAL PULL-UP = 10 A
V
A
BATT
RESET Output Voltage vs
= 25 C
as low as 1V.
= 0V
1
Supply Voltage
SUPPLY VOLTAGE (V)
2
3
4
690 TA02
1
5

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LTC690 Summary of contents

Page 1

... In addition, the RESET output is guaranteed to remain logic low even with V The LTC690 family powers the active CMOS RAMs with a charge pumped NMOS power switch to achieve low drop- out and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, powers the RAMs in standby through an efficient PMOS switch ...

Page 2

... V Output Current ................. Short-Circuit Protected OUT Power Dissipation ............................................. 500mW Operating Temperature Range + 0.3V) LTC690/91/94/95C ............................... OUT LTC690/91/94/95I ........................... – LTC690M ...................................... – 125 C Storage Temperature Range ................ – 150 C Lead Temperature (Soldering, 10 sec.)................ 300 (Note 3) ORDER PART NUMBER ...

Page 3

... BATT ON Output Voltage (Note 4) BATT ON Output Short-Circuit Current (Note 4) Reset and Watchdog Timer Reset Voltage Threshold Reset Threshold Hysteresis Reset Active Time (LTC690/91) (Note 5) Reset Active Time (LTC694/95) (Note 5) Watchdog Time-Out Period, Internal Oscillator Watchdog Time-Out Period, External Clock (Note 6) Reset Active Time PSRR ...

Page 4

... Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and RESET have weak internal pull-ups of typically 3 A. However, external pull-up resistors may be used when higher speed is required. Note 5: The LTC690 and LTC691 have minimum reset active time of 35ms (50ms typically) while the LTC694 and LTC695 have longer minimum 4 ...

Page 5

... The power failure CC BATT , is delivered to V output remains high when PFI is above 1.3V and goes low OUT when PFI is below 1.3V. Connect PFI to GND not used. LTC690/LTC691 LTC694/LTC695 V OUT BATT ON LOW LINE CE OUT PFO RESET RESET WDO ...

Page 6

... RESET goes active low. After V BATT returns to 5V, reset pulse generator forces RESET to remain active low for a minimum of 35ms for the LTC690 /LTC691 (140ms for the LTC694/LTC695). When the watchdog timer is enabled but not serviced prior to a preset time-out period, reset pulse generator also forces ...

Page 7

... OUT OUT 5. 2.8V BATT 4.95 4.90 SLOPE = 5 4.85 4.80 4. LOAD CURRENT (mA) 690 G01 Reset Active Time vs Temperature LTC690 100 125 – 50 – TEMPERATURE ( C) 690 G04 Power-Fail Comparator Response Time ...

Page 8

... PMOS switch, M2. C2 has typically 20mV of hysteresis to prevent spurious switching when V equal During normal operation, the LTC690 family uses a charge pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to pin do not ...

Page 9

... PPLICATI S I FOR ATIO of external PNP transistor (Figure 2). If higher currents are needed with the LTC690 and LTC694, a high current Schottky diode can be connected from the V V pin to supply the extra current. OUT ANY PNP POWER TRANSISTOR 5 BATT ...

Page 10

... CE IN can be derived from the microprocessor’s address LTC690 LTC691 decoder output. Figure 6 shows a typical nonvolatile LTC694 CMOS RAM application. LTC695 Memory protection can also be achieved with the LTC690 GND and LTC694 by using RESET as shown in Figure 7. 690 F04 Table 1. Input and Output Status in Battery Back-Up Mode SIGNAL STATUS ...

Page 11

... FROM DECODER RESET 3V GND RESET TO P Figure 6. A Typical Nonvolatile CMOS RAM Application OUT + 0 LTC690 LTC694 V RESET BATT 3V GND Figure 7. Write Protect for RAM with LTC690 or LTC694 LT1086 OUT + + 0.1 F ADJ 10 F 100 10k R1 300k 51k R2 10k Figure 8 ...

Page 12

... WDI after RESET . is inactive. The watchdog time-out period is fixed at 1.0 IN second minimum on the LTC690 and LTC694. Figure 11 shows the timing diagram of watchdog time-out period and reset active time. The watchdog time-out period is restarted as soon as RESET is inactive. When either a high- ...

Page 13

... OSC SEL 5V 7 OSC IN 8 FLOATING 5V OSC SEL OR HIGH 7 FLOATING OSC IN OR HIGH Figure 12. Oscillator Configurations LTC690/LTC691 LTC694/LTC695 690 F11 EXTERNAL OSCILLATOR OSC SEL CC LTC691 LTC695 4 7 GND OSC IN INTERNAL OSCILLATOR 100ms WATCHDOG 3 8 FLOATING V OSC SEL ...

Page 14

... Floating or High *The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is f Push-Button Reset The LTC690 family does not provide a logic input for direct connection to a pushbutton. However, a push-button in series with a 100 resistor connected to the RESET output pin (Figure 13) provides an alternative for manual reset. ...

Page 15

... TYP (LTC DWG # 05-08-1510) 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.018 0.003 0.100 0.010 (2.540 0.254) (0.457 0.076) LTC690/LTC691 LTC694/LTC695 (LTC DWG # 05-08-1110) 0.405 (10.287) 0.005 0.200 MAX (5.080) (0.127) MIN MAX 8 7 ...

Page 16

... CC V OUT 0.1 F 0.1 F LTC691 LTC695 V BATT LOW LINE 3V GND LTC690 TA03 U Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.037 – 0.045 0.093 – 0.104 (0.940 – 1.143) (2.362 – 2.642) 0.050 (1.270) TYP 0.014 – ...

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