LTC690 Linear Technology, LTC690 Datasheet - Page 10

• Manufacturer Part Number: LTC690
• Description: Microprocessor Supervisory Circuits
• Manufacturer: Linear Technology

LTC690/LTC691
LTC694/LTC695
A
If battery connections are made through long wires, a 10
to 100 series resistor and a 0.1 F capacitor are recom-
mended to prevent any overshoot beyond V
lead inductance (Figure 4).
Memory Protection
The LTC691 and LTC695 include memory protection
circuitry that ensures the integrity of the data in memory
by preventing write operations when V
Two additional pins, CE IN and CE OUT, control the Chip
Enable or Write inputs of CMOS RAM. When V
OUT follows CE IN with a typical propagation delay of
20ns. When V
V
10
Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
V
BATT
BATT
PPLICATI
Figure 4. 10 /0.1 F Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement
, CE OUT is forced high, independent of CE IN. CE
to GND and V
CC
10
CE OUT
O
falls below the reset voltage threshold or
CE IN
V
CC
V
U
OUT
OUT
S
= V
4.3M
to V
BATT
I FOR ATIO
U
CC
.
0.1 F
W
Figure 5. Timing Diagram for CE IN and CE OUT
CC
V
BATT
LTC690
LTC691
LTC694
LTC695
is at invalid level.
GND
CC
690 F04
CC
due to the
U
is 5V, CE
V1
V2
OUT is an alternative signal to drive the CE, CS, or Write
input of battery-backed up CMOS RAM. CE OUT can also
be used to drive the Store or Write input of an EEPROM,
EAROM or NOVRAM to achieve similar protection. Figure
5 shows the timing diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile
CMOS RAM application.
Memory protection can also be achieved with the LTC690
and LTC694 by using RESET as shown in Figure 7.
SIGNAL
V
V
V
BATT ON
PFI
PFO
RESET
RESET
LOW LINE Logic low
WDI
WDO
CE IN
CE OUT
OSC IN
OSC SEL
Table 1. Input and Output Status in Battery Back-Up Mode
CC
OUT
BATT
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
STATUS
C2 monitors V
V
The supply current is 1 A maximum.
Logic high. The open-circuit output voltage is equal to V
Power failure input is ignored.
Logic low
Logic low
Logic high. The open-circuit output voltage is equal to V
Watchdog input is ignored.
Logic high. The open-circuit output voltage is equal to V
Chip Enable Input is ignored.
Logic high. The open-circuit output voltage is equal to V
OSC IN is ignored.
OSC SEL is ignored.
OUT
is connected to V
CC
for active switchover.
BATT
through an internal PMOS switch.
V
OUT
= V
690 F05
BATT
OUT
OUT
OUT
OUT
.
.
.
.