RM5231A PMC-Sierra Inc, RM5231A Datasheet - Page 16

• Manufacturer Part Number: RM5231A
• Description: 64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
3.11 System Control Coprocessor (CP0)
3.12 System Control Co-Processor Registers
The system control coprocessor, also called coprocessor 0 or CP0 in the MIPS architecture, is
responsible for the virtual memory sub-system, the exception control system, and the diagnostics
capability of the processor.
The memory management unit controls the virtual memory system page mapping. It consists of an
instruction address translation buffer, ITLB, a data address translation buffer, DTLB, a Joint
instruction and data address translation buffer, JTLB, and co-processor registers used by the virtual
memory mapping sub-system.
The RM5231A incorporates all system control coprocessor (CP0) registers on-chip. These
registers provide the path through which the virtual memory system’s page mapping is examined
and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RM5231A includes registers to
implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data
error detection.
Figure 4 shows the CP0 registers.
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
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