RM5231A PMC-Sierra Inc, RM5231A Datasheet - Page 24

• Manufacturer Part Number: RM5231A
• Description: 64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
3.26 Enhanced Write Modes
Figure 7 Processor Block Read
Figure 8 Processor Block Write
The RM5231A implements two enhancements to the original R4000 write mechanism: Write
Reissue and Pipeline Writes. The original R4000 allowed a write address cycle on the SysAD bus
only once every four SysClock cycles. Hence for a non-block write, this meant that two out of
every four cycles were wait states.
Pipelined write mode eliminates these two wait states by allowing the processor to drive a new
write address onto the bus immediately after the previous write data cycle. This allows for higher
SysAD bus utilization. However, at high bus frequencies the processor may drive a subsequent
write onto the bus prior to the time the external agent deasserts WrRdy*, indicating that it can not
accept another write cycle. This can cause the write cycle to be missed.
Write reissue mode is an enhancement to pipelined write mode and allows the processor to reissue
missed write cycles. If WrRdy* is deasserted during the issue phase of a write operation, the cycle
is aborted by the processor and reissued at a later time.
SysAD
SysClock
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
SysClock
SysAD
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Addr
Read
Write
Addr
NData
Data0
Data1
NData
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
NData
Data2
NData
Data0
NData
Data3
NData
Data1
NData
Data4
Data2
NData
NData
Data5
NData
Data3
NData
Data6
NData
Data4
NEOD
Data7
NData
Data5
NData
Data6
NEOD
Data7
Preliminary
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