RM5261A-250-H PMC-Sierra Inc, RM5261A-250-H Datasheet - Page 16

• Manufacturer Part Number: RM5261A-250-H
• Description: RM5261A Microprocessor with 64-Bit System Bus Data Sheet Preliminary
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
3.11 System Control Co-processor (CP0)
3.12 System Control Co-Processor Registers
The system control coprocessor, also called coprocessor 0 or CP0 in the MIPS architecture, is
responsible for the virtual memory sub-system, the exception control system, and the diagnostics
capability of the processor. In the MIPS architecture, the system control co-processor (and thus the
kernel software) is implementation dependent.
The memory management unit controls the virtual memory system page mapping. It consists of an
instruction address translation buffer, ITLB, a data address translation buffer, DTLB, a Joint
instruction and data address translation buffer, JTLB, and co-processor registers used by the virtual
memory mapping sub-system.
The RM5261A incorporates all system control co-processor (CP0) registers on-chip. These
registers provide the path through which the virtual memory system’s page mapping is examined
and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RM5261A includes registers to
implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data
error detection.
Figure 4 shows the CP0 registers.
Figure 4 CP0 Registers
* Register number
LLAddr
17*
47
0
PageMask
EntryHi
TagLo
10*
28*
(entries protected
5*
from TLBWR)
TLB
Used for memory
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
management
EntryLo0
EntryLo1
2*
3*
TagHi
29*
Random
Config
Wired
Index
PRId
15*
16*
0*
1*
6*
Context
Status
Count
ECC
EPC
12*
14*
26*
4*
9*
Used for exception
BadVAddr
ErrorEPC
Compare
XContext
CacheErr
Cause
processing
13*
20*
27*
30*
11*
8*
Preliminary
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