ph5330e NXP Semiconductors, ph5330e Datasheet
ph5330e
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ph5330e Summary of contents
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... PH5330E N-channel TrenchMOS logic level FET Rev. 02 — 19 October 2009 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. ...
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... Figure °C mb ≤ 10 µs; pulsed ° ° 36 j(init) D ≤ unclamped 0.15 ms sup p Rev. 02 — 19 October 2009 PH5330E Graphic symbol mbb076 Version SOT669 Min Max - 30 - 50.8 and Figure 3 - 250 - 62 ...
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... T (°C) mb Fig 2. Normalized total power dissipation as a function of mounting base temperature = Rev. 02 — 19 October 2009 PH5330E N-channel TrenchMOS logic level FET 03aa15 50 100 150 200 T (°C) mb 003aaa477 = 10 μ 100 μ 100 ms ...
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... Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration PH5330E_2 Product data sheet N-channel TrenchMOS logic level FET Conditions see Figure 4 −3 − Rev. 02 — 19 October 2009 PH5330E Min Typ Max Unit - - 2 K/W 003aaa478 t p δ ...
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... Figure /dt = -50 A/µ ° /dt -50 A/µ ° Rev. 02 — 19 October 2009 PH5330E N-channel TrenchMOS logic level FET Min Typ Max 0 1.7 2 500 - 0 0 ...
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... V GS(th) (V) 2 max 1 0 − (V) GS Fig 8. Gate-source threshold voltage as a function of junction temperature Rev. 02 — 19 October 2009 PH5330E N-channel TrenchMOS logic level FET 003aaa480 25 °C = 150 ° (V) GS 003aaa414 max typ min 120 0 ...
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... C (pF − (nC) G Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values Rev. 02 — 19 October 2009 PH5330E N-channel TrenchMOS logic level FET 03aa27 0 60 120 180 ( ° 003aaa482 C iss C oss C rss 2 1 ...
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... Fig 13. Source current as a function of source-drain voltage; typical values PH5330E_2 Product data sheet ( °C = 150 ° 0.2 0.4 0.6 0.8 Rev. 02 — 19 October 2009 PH5330E N-channel TrenchMOS logic level FET 003aaa483 1 V (V) SD © NXP B.V. 2009. All rights reserved ...
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... D 1 (1) ( max 4.41 2.2 0.9 0.25 0.30 4.10 5.0 4.20 3.62 2.0 0.7 0.19 0.24 3.80 4.8 REFERENCES JEDEC JEITA MO-235 Rev. 02 — 19 October 2009 PH5330E N-channel TrenchMOS logic level FET detail ( 3.3 6.2 0.85 1.3 1.3 1.27 0.25 3.1 5.8 0.40 0.8 0.8 EUROPEAN ISSUE DATE ...
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... Legal texts have been adapted to the new company name where appropriate. PH5330E-01 20040109 (9397 750 12334) PH5330E_2 Product data sheet N-channel TrenchMOS logic level FET Data sheet status Change notice Product data sheet - Product data - Rev. 02 — 19 October 2009 PH5330E Supersedes PH5330E-01 - © NXP B.V. 2009. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 19 October 2009 PH5330E N-channel TrenchMOS logic level FET © NXP B.V. 2009. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PH5330E All rights reserved. Date of release: 19 October 2009 Document identifier: PH5330E_2 ...