cy28446 Cypress Semiconductor Corporation., cy28446 Datasheet
cy28446
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cy28446 Summary of contents
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... REF VDD_PCI 47 REF 46 VSS_REF 45 XIN 44 XOUT 43 VDD_REF 42 SDATA 41 SCLK CY28446 40 CPU_STOP# 39 CPUT0 38 CPUC0 37 VSS_CPU 36 VDD_CPU 35 CPUT1 34 CPUC1 33 VSS_SRC • 198 Champion Court • San Jose CY28446 ® Calistoga Chipset DOT96 48M 95134-1709 • 408-943-2600 Revised April 03, 2006 [+] Feedback ...
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... Hi-Z Hi-Z Hi-Z Hi-Z REF/8 REF/24 REF REF/8 REF/24 REF CY28446 LCD DOT96 USB 100 96 48 100 96 48 100 96 48 100 96 48 100 96 48 Hi-Z Hi-Z Hi-Z REF/8 REF REF REF/8 REF REF Page ...
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... IMFS_C Refer to DC Electrical Specifications table for V tions. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. when in test mode 0 = Tri-state Ref/N Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. CY28446 ,V ,V specifica- ILFS_C IMFS_C IHFS_C Page ...
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... Acknowledge from slave 37:30 Byte Count from slave – 8 bits 38 Acknowledge 46:39 Data byte 1 from slave – 8 bits 47 Acknowledge 55:48 Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop CY28446 Page [+] Feedback ...
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... Byte Read Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop CY28446 Page [+] Feedback ...
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... Spread on (–0.5% spread spectrum on CPU/SRC/PCI clocks) Description Reserved set to 1 Reserved set to 1 PCI3 Output Enable 0 = Disable Enable PCI2 Output Enable 0 = Disable Enable PCI1Output Enable 0 = Disable Enable PCI0 Output Enable 0 = Disable Enable Reserved set to 1 Reserved set to 1 CY28446 Page [+] Feedback ...
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... SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted Tri-state when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted Tri-state when PD asserted CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted Tri-state when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted Tri-state when PD asserted CY28446 Page [+] Feedback ...
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... Disable (Tri-state Enable Reserved set to 0 Allow control of SRC[T/C]10 with assertion of OEA Free running Stopped with OEA# Allow control of SRC[T/C]9 with assertion of OEB Free running Stopped with OEB# Allow control of SRC[T/C]8 with assertion of OEA Free running Stopped with OEA# CY28446 Page [+] Feedback ...
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... AT Parallel The CY28446 requires a Parallel Resonance Crystal. Substi- tuting a series resonance crystal will cause the CY28446 to operate at the wrong frequency and violate the ppm specifi- cation. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect ...
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... In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 µs after asserting Vtt_PwrGd#. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. CY28446 Page [+] Feedback ...
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... Figure example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. Tstable <1.8 ms Tdrive_PWRDN# <300 µσ, >200 mV CY28446 Page [+] Feedback ...
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... The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. Tdrive_CPU_STP#,10 ns > 200 mV Figure 6. CPU_STP# Deassertion Waveform Figure 8. CPU_STP# Assertion Waveform CY28446 1.8 ms Page [+] Feedback ...
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... The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transi- ). (See tions to a high level. SU Tsu Figure 10. PCI_STP# Assertion Waveform Tdrive_SRC Tsu Figure 11. PCI_STP# Deassertion Waveform CY28446 1.8mS Page [+] Feedback ...
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... Sample Sels Delay VTT_PW RGD# State 1 State 2 On Figure 12. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay >0.25mS S3 VDD_A = off Normal Operation VTT_PWRGD# = toggle CY28446 Device is not affected, VTT_PW RGD# is ignored State Sample Inputs straps Wait for <1.8ms Enable Outputs Page [+] Feedback ...
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... Except internal pull-up resistors, 0 < < Except internal pull-down resistors, 0 < V < – max. load and freq. per Figure 15 PD asserted, Outputs Driven PD asserted, Outputs Tri-state CY28446 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD –65 150 ° ° ...
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... Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured from V = 0.175 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 15 CY28446 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10.0 ns – 500 ps – 300 ppm 9.997001 10.00300 ns 7 ...
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... Measured at crossing point V OX Measured at crossing point V OX Measured from V = 0.175 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 15 Math averages Figure 15 CY28446 Min. Max. Unit –150 – mV [1] 250 550 mV – HIGH 0.3 –0.3 – V – 0.2 ...
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... Measurement at 1.5V Measurement at 1.5V Measured at crossing point V OX Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point V OX Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V CY28446 Min. Max. Unit – HIGH 0.3 –0.3 – V – 0 29.99100 30.00900 ns 29 ...
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... T M easurem ent 100 ohm D ifferential L2 T PCB Package Type CY28446 point M easurem ent point Product Flow Commercial, 0 ° ° C Commercial, 0 ° ° C Page [+] Feedback ...
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... Cypress against all charges. 0.08[0.003] C 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.30[0.012] 0.50[0.020] 0°-12° C SEATING PLANE SIDE VIEW CY28446 0.18[0.007] 0.28[0.011] PIN1 ID 0.20[0.008 0.45[0.018] E-PAD (PAD SIZE VARY BY DEVICE TYPE) 0.24[0.009] (4X) ...
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... Document History Page Document Title: CY28446 Clock Generator for Intel Document Number: 001-00168 Orig. of REV. ECN NO. Issue Date Change ** 366781 See ECN *A 385257 See ECN *B 391184 See ECN *C 402318 See ECN *D 436731 See ECN Document #: 001-00168 Rev *D ® Calistoga Chipset Description of Change ...