cy28351-400 SpectraLinear Inc, cy28351-400 Datasheet - Page 2

• Manufacturer Part Number: cy28351-400
• Description: Differential Clock Buffer/driver
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 28, 2006
Pin Description
Zero Delay Buffer
When used as a zero delay buffer, the CY28351-400 will likely
be in a nested clock tree application. For these applications
the CY28351-400 offers a clock input as a PLL reference. The
CY28351-400 then can lock onto the reference and translate
with near zero delay to low skew outputs. For normal
operation, the external feedback input, FBIN, is connected to
the feedback output, FBOUT. By connecting the feedback
output to the feedback input the propagation delay through the
Function Table
1, 7, 8, 18, 24, 25,
Notes:
46, 44, 39, 29, 27
47, 43, 40, 30, 26
4, 21, 28, 34, 38,
1. A bypass capacitor (0.1μF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
2. Each output pair can be three-stated via the two-line serial interface.
3, 5, 10, 20, 22
2, 6, 9, 19, 23
31, 41, 42, 48
Pin Number
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
14, 32,36
V
GND
GND
2.5V
2.5V
2.5V
DDA
13
35
33
12
37
11
45
16
15
17
Input
[1]
Pin Name
< 20 MHz
YT(0:9)
YC(0:9)
FBOUT
SDATA
CLKIN
VDDQ
AVDD
SCLK
AVSS
VDDI
CLKIN
FBIN
VDD
VSS
NC
H
H
L
L
I/O
I/O
O
O
O
–
I
I
I
Clock Input.
Feedback Clock Input. Connect to FBOUT for
accessing the PLL.
Clock Outputs.
Clock Outputs.
Feedback Clock Output. Connect to FBIN for
normal operation. A bypass delay capacitor at this
output will control Input Reference/Output Clocks
phase relationships.
Serial Clock Input. Clocks data at SDATA into the
internal register.
Serial Data Input. Input data is clocked to the
internal register to enable/disable individual outputs.
This provides flexibility in power management.
2.6V Power Supply for Logic.
2.6V Power Supply for Output Clock Buffers.
2.6V Power Supply for PLL.
2.6V Power Supply for Two-line Serial Interface. 2.6V Nominal
Common Ground.
Analog Ground.
Not Connected.
YT(0:9)
Hi-Z
H
H
L
L
[2]
Pin Description
Outputs
device is eliminated. The PLL works to align the output edge
with the input reference edge thus producing a near zero
delay. The reference frequency affects the static phase offset
of the PLL and thus the relative delay between the inputs and
outputs.
When V
bypassed for test purposes.
YC(0:9)
Hi-Z
H
H
L
L
[2]
DDA
is strapped LOW, the PLL is turned off and
FBOUT
Hi-Z
H
H
L
L
Input
Input
Differential Outputs
Output
Data Input for the two-line serial
bus
Data Input and Output for the
two-line serial bus
2.6V Nominal
2.6V Nominal
2.6V Nominal
0.0V Ground
0.0V Analog Ground
Electrical Characteristics
CY28351-400
BYPASSED/OFF
BYPASSED/OFF
PLL
Page 2 of 7
On
On
Off