cy28351-400 SpectraLinear Inc, cy28351-400 Datasheet - Page 4

• Manufacturer Part Number: cy28351-400
• Description: Differential Clock Buffer/driver
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 28, 2006
Maximum Operating Conditions
Input Voltage Relative to V
Input Voltage Relative to V
Storage Temperature: ................................. –65°C to +150°C
Operating Temperature:................................ –40°C to +85°C
Maximum Power Supply: ................................................ 3.5V
DC Electrical Specifications
AC Electrical Specifications
All V
V
V
V
V
V
I
V
V
V
V
I
I
ID
I
C
f
t
t
T
t
t
t
t
t
t
Notes:
Parameter
10. All differential input and output terminals are terminated with 120Ω/16 pF, as shown in Figure 7.
11. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
IN
OZ
DDQ
DD
CLK
DC
LOCK
CCJ
tjit(h-per)
PLH
PHL
SKEW
PHASE
PHASEJ
Parameter
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. unused inputs must be held HIGH or LOW to prevent them from floating.
5. For load conditions, see Figure 7.
6. The value off VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 7.
7. All outputs switching loaded with 16 pF in 60Ω environment. See Figure 7.
8. Parameters are guaranteed by design and characterization. Not 100% tested in production
9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down
IL
IH
IL
IH
ID
OL
OH
OUT
OC
R
IN
STAT
T
spread of –0.5%.
F
DD’s
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Output Clocks Slew Rate
Cycle to Cycle Jitter
Half-period jitter
LOW-to-HIGH Propagation Delay, CLKIN to YT
HIGH-to-LOW Propagation Delay, CLKIN to YT
Any Output to Any Output Skew
Phase Error
Phase Error Jitter
Supply Voltage
Input Low Voltage
Input High Voltage
Input Voltage Low
Input Voltage High
Differential Input Voltage
Input Current
Output Low Voltage
Output High Voltage
Output Voltage Swing
Output Crossing Voltage
High-Impedance Output Current
Dynamic Supply Current
Static Supply Current
PLL Supply Current
Input Pin Capacitance
Description
[10]
SS
DDQ
[11]
:...............................V
Description
or AV
[11]
[5]
[4]
[8,9]
DD
[6]
[7]
: ............. V
[10]
[3]
Operating
SDATA , SCLK
SDATA , SCLK
CLKIN, FBIN
CLKIN, FBIN
CLK, FBIN
V
V
V
V
All V
A
VDD only
IN
DDQ
DDQ
O
DD
SS
= GND or V
= 0V or V
DDQ
+ 0.3V
– 0.3V
= 2.375V, I
= 2.375V, I
and V
V
20% to 80% of V
f > 66 MHz
f > 66 MHz
f > 66 MHz
Condition
IN
DD
DDI
O
= V
, A
OL
OH
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
the range:
V
Unused inputs must always be tied to an appropriate logic
voltage level (either V
= V
, F
SS
VDD
DDQ
= 12 mA
= –12 mA
DDQ
O
< (V
Condition
, V
= 273MHz
, CLKT, FBIN
DDQ
IN
or V
OD
= 2.5V to 2.7V
OUT
) < V
SS
(V
0.6V
IN
– 0.15
DD
Min.
0.36
DDQ
or V
–10
–10
2.5
2.2
1.7
1.1
and V
–
–
–
–
–
–
–
.
DDQ
/2)
DD
–150
Min.
–75
–75
–50
1.5
1.5
60
40
1
–
).
–
OUT
V
Typ.
DDQ
CY28351-400
235
should be constrained to
–
–
–
–
–
–
–
–
–
–
–
9
4
/2
Typ.
3.5
3.5
–
–
–
–
–
–
–
–
V
V
0.3V
(V
DDQ
DDQ
+ 0.15
Page 4 of 7
Max.
DDQ
300
2.7
1.0
0.6
10
10
12
–
–
–
1
6
Max.
DDQ
+ 0.6
273
100
100
150
– 0.4
60
75
75
50
3
6
6
/2)
Unit
MHz
V/ns
Unit
mA
mA
mA
μA
μA
pF
μs
ps
ps
ns
ns
ps
ps
ps
V
V
V
V
V
V
V
V
V
V
%