ds26518 Maxim Integrated Products, Inc., ds26518 Datasheet - Page 167

• Manufacturer Part Number: ds26518
• Description: 8-port T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts. See
Bit 7: Loss of Receive Clock Condition Clear (LORCC). Falling edge detect of LORC. Set when an LORC
condition was detected and then removed.
Bit 6: Spare Code Detected Condition Clear (LSPC). Falling edge detect of LSP. Set when a spare-code match
condition was detected and then removed.
Bit 5: Loop Down Code Detected Condition Clear (LDNC). Falling edge detect of LDN. Set when a loop-down
condition was detected and then removed
Bit 4: Loop Up Code Detected Condition Clear (LUPC). Falling edge detect of LUP. Set when a loop-up
condition was detected and then removed.
Bit 3: Loss of Receive Clock Condition Detect (LORCD). Rising edge detect of LORC. Set when the RCLKn pin
has not transitioned for one channel time.
Bit 2: Spare Code Detected Condition Detect (LSPD). Rising edge detect of LSP. Set when the spare code as
defined in the
Bit 1: Loop Down Code Detected Condition Detect (LDND). Rising edge detect of LDN. Set when the loop down
code as defined in the
Bit 0: Loop Up Code Detected Condition Detect (LUPD). Rising edge detect of LUP. Set when the loop up code
as defined in the
LORCC
T1RSCD1:T1RSCD2
7
0
T1RUPCD1:T1RUPCD2
T1RDNCD1:T1RDNCD2
RLS3 (T1 Mode)
Receive Latched Status Register 3
092h + (200h x (n - 1)) : where n = 1 to 8
LSPC
6
0
registers is being received.
LDNC
5
0
register is being received.
register is being received.
167 of 286
LUPC
4
0
RLS3
LORCD
3
0
for E1 Mode.
DS26518 8-Port T1/E1/J1 Transceiver
LSPD
2
0
LDND
1
0
LUPD
0
0