upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 243

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

6.4 PLL Function
The PLL function is used to output the operating clock of the CPU and peripheral macro at a frequency
10 times (PLL1) / 12 times (PLL0) higher than the oscillation frequency, and selects the clock-through
mode.
•
•
PLL0 can generate below frequencies from f
Note: Set the f
When PLL function is used:
Clock-through mode:
Base clock (f
PLL0
f
X
as 24 MHz or 32 MHz when f
X
)
OCKS0 register
divide value
User’s Manual U16702EE3V2UD00
1
2
3
4
5
Input clock:
Output:
Input clock:
Output:
Chapter 6 Clock Generator
X
PLL0 Time
signal and register setting:
value
12
PLL0
4 to 8 MHz
4 to 40 MHz (µPD70F3403 and µPD70F3403A)
4 to 32 MHz (µPD70F3402)
4 to 8 MHz
4 to 8 MHz
is used as CPU clock.
CKC Register
divide value
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
f
PLL0
f
f
f
f
f
f
PLL0
PLL0
PLL0
PLL0
PLL0
f
f
f
f
f
f
PLL0
f
f
PLL0 Output
PLL0
PLL0
PLL0
PLL0
PLL0
PLL0
PLL0
PLL0
(f
PLL0
= f
= f
= f
= f
= f
= f
= f
= f
= f
= f
= f
= f
= f
= f
= f
X
)
X
X
X
X
X
X
Note
X
X
X
X
X
X
X
X
× 0.75
× 2.4
× 0.6
× 1.5
× 1.5
× 1.2
× 12
× 6
× 3
× 4
× 2
× 1
× 3
× 6
× 3
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