upd78f0103 Renesas Electronics Corporation., upd78f0103 Datasheet - Page 456

• Manufacturer Part Number: upd78f0103
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

456
Main clock
Function
MCM: Main clock
mode register
MOC: Main OSC
control register
OSTC:
Oscillation
stabilization time
counter status
register
OSTS: Oscillation
stabilization time
select register
Details of
Function
When the Ring-OSC clock is selected as the clock to be supplied to the CPU,
the divided clock of the Ring-OSC oscillator output (f
peripheral hardware (f
hardware with the Ring-OSC clock cannot be guaranteed. Therefore, when
the Ring-OSC clock is selected as the clock supplied to the CPU, do not use
peripheral hardware. In addition, stop the peripheral hardware before
switching the clock supplied to the CPU from the X1 input clock to the Ring-
OSC clock. Note, however, that the following peripheral hardware can be
used when the CPU operates on the Ring-OSC clock.
• Watchdog timer
• Clock monitor
• 8-bit timer H1 when f
• Peripheral hardware with an external clock selected as the clock source
(Except when the external count clock of TM00 is selected (TI000 valid edge))
Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before
setting MSTOP.
After the above time has elapsed, the bits are set to 1 in order from MOST11
and remain 1.
If the STOP mode is entered and then released while the Ring-OSC clock is
being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
The wait time when STOP mode is released does not include the time after
STOP mode release until clock oscillation starts (“a” below) regardless of
whether STOP mode is released by RESET input or interrupt generation.
To set the STOP mode when the X1 input clock is used as the CPU clock, set
OSTS before executing the STOP instruction.
Execute the OSTS setting after confirming that the oscillation stabilization time
has elapsed as expected in the OSTC.
If the STOP mode is entered and then released while the Ring-OSC clock is
being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
The wait time when STOP mode is released does not include the time after
STOP mode release until clock oscillation starts (“a” below) regardless of
whether STOP mode is released by RESET input or interrupt generation.
by OSTS
by OSTS
APPENDIX D LIST OF CAUTIONS
User’s Manual U15836EJ5V0UD
X
R
= 240 kHz (TYP.)). Operation of the peripheral
/2
7
is selected as the count clock
Cautions
X
) is supplied to the
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