upd78f0103 Renesas Electronics Corporation., upd78f0103 Datasheet - Page 50

no-image

upd78f0103

Manufacturer Part Number
upd78f0103
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
upd78f0103HMC-5A4-A
Manufacturer:
NEC
Quantity:
20 000
Part Number:
upd78f0103M6MC-5A4
Manufacturer:
NEC
Quantity:
312
3.2 Processor Registers
3.2.1 Control registers
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
(2) Program status word (PSW)
50
78K0/KB1 products incorporate the following processor registers.
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are reset upon execution of the RETB, RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
(a) Interrupt enable flag (IE)
(b) Zero flag (Z)
PC
This flag controls the interrupt request acknowledgment operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and maskable interrupt requests are all
disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment enable is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
PC15 PC14 PC13 PC12 PC11 PC10 PC9
15
PSW
Figure 3-10. Format of Program Status Word
IE
7
Figure 3-9. Format of Program Counter
CHAPTER 3 CPU ARCHITECTURE
Z
User’s Manual U15836EJ5V0UD
RBS1
PC8
AC
PC7
RBS0
PC6
0
PC5
ISP
PC4
PC3
CY
0
PC2
PC1 PC0
0

Related parts for upd78f0103