sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 162
sc9s12hy64j0vllr
Manufacturer Part Number
sc9s12hy64j0vllr
Description
S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.SC9S12HY64J0VLLR.pdf
(792 pages)
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Background Debug Module (S12SBDMV1)
5.2
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode.
5.3
5.3.1
Table 5-1
162
External Signal Description
Memory Map and Register Definition
shows the BDM memory map when BDM is active.
Module Memory Map
0x3_FF0C–0x3_FF0E
0x3_FF00–0x3_FF0B
0x3_FF10–0x3_FFFF
Global Address
0x3_FF0F
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 5-1. BDM Memory Map
Family ID (part of BDM firmware ROM)
BDM firmware ROM
BDM firmware ROM
BDM registers
Module
Freescale Semiconductor
(Bytes)
Size
240
12
3
1
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