sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 494
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sc9s12hy64j0vllr
Manufacturer Part Number
sc9s12hy64j0vllr
Description
S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.SC9S12HY64J0VLLR.pdf
(792 pages)
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Timer Module (TIM16B8CV2) Block Description
14.3.2.4
Read: Anytime
Write: Anytime
14.3.2.5
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
Read: Anytime
494
Module Base + 0x0003
Module Base + 0x0004
Module Base + 0x0005
OC7D[7:0]
Reset
Reset
Reset
Field
7:0
W
W
W
R
R
R
TCNT15
OC7D7
TCNT7
Output Compare 7 Data — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the
timer port data register depending on the output compare 7 mask register.
Output Compare 7 Data Register (OC7D)
Timer Count Register (TCNT)
15
0
0
0
7
7
TCNT14
OC7D6
TCNT6
14
0
0
0
6
6
Figure 14-9. Output Compare 7 Data Register (OC7D)
Figure 14-10. Timer Count Register High (TCNTH)
Figure 14-11. Timer Count Register Low (TCNTL)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 14-5. OC7D Field Descriptions
TCNT13
OC7D5
TCNT5
13
0
0
0
5
5
TCNT12
OC7D4
TCNT4
12
0
0
0
4
4
Description
TCNT11
OC7D3
TCNT3
11
0
0
0
3
3
TCNT10
OC7D2
TCNT2
10
0
0
0
2
2
OC7D1
TCNT9
TCNT1
Freescale Semiconductor
0
0
0
1
9
1
OC7D0
TCNT8
TCNT0
0
0
0
0
9
0
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