sc26c94 NXP Semiconductors, sc26c94 Datasheet - Page 20

• Manufacturer Part Number: sc26c94
• Description: Quad Universal Asynchronous Receiver/transmitter Quart
• Manufacturer: NXP Semiconductors

Philips Semiconductors
I/O Port Control Channel B (IOPCRB)
I/O Port Control Channel C (IOPCRC)
I/O Port Control Channel D (IOPCRD)
The input part of the I/O pins is always active. The programming of the IOPCR bits to 00 merely turns off the out drivers and places
the pin at high impedance.
A read of the IPR register returns the value of the IPR bits as shown above. IPR(5) is at bit position 5 of the data bus. Note that the IPR bit
positions do not follow the 0, 1, 2, 3 order of the I/O ports. During a read of the IPR the I/O ports are not latched. Therefore, it is possible to see
changing data during the read. Port pins that have clocks on them may not yield valid data during the read.
Since the input circuits of the I/O ports are always active it is possible to direct the port signal back into the port. For example: I/O1 will output
the RTS signal. Setting the Counter/Timer (C/T) to be clocked by the I/O1 port will result in the counter counting the number of times RTS goes
active. The change of state detectors on I/O0 and I/O1 will, when programmed, always be sensitive to the signal on the port regardless of the
source of that port’s signal.
NOTES:
1. Normal configurations place RTSN output on I/O1 and place Tx external clock input on I/O3. For the 48 pin Dual In-Line package, I/O3 is
2. I/O1 becomes RTSN when IOPCR(3:2) = 01 and MR1(7) = 1 and OPR(1) = 1. (OPR(3) for channel B)
Registers of the Interrupt System
The CIR, and “Global” registers are updated with the IACKN signal
or from the “Update CIR” command at hex address 2A. These
registers are not updated when IRQN is asserted since there could
be a long time between the assertion of IRQN and the start of the
interrupt service routine. (See notes following this section).
Current Interrupt Register (CIR)
The Channel # field indicates which of the four UARTs has the
highest priority interrupt currently outstanding, while the Type field
1995 May 1
00 = input
01 = output
10 = output
11 = output
00 = input
01 = output
10 = output
11 = output
00 = input
01 = output
10 = output
11 = output
Pin Control Bits
Pin Control Bits
Pin Control Bits
Pin Control Bits
Pin Control Bits
Pin Control Bits
Quad universal asynchronous receiver/transmitter (QUART)
not available. The following options allow flexible I/O programming with the 48 pin package:
IOPCR[xx]
IOPCR[xx]
IOPCR[xx]
IOPCR[xx]
IOPCR[xx]
IOPCR[xx]
# Bytes
3
IPR(7), TxC in
OPRab(7)
TxC 16x
TxC 1x
IPR(5), TxC in
OPRcd(5)
TxC 16x
TxC 1x
IPR(7), TxC in
OPRcd(7)
TxC 16x
TxC 1x
When IOPCR(7:6), the I/O3 control,
When IOPCR(5:4), the I/O2 control, = 01, then I/O2 may be the RTSN signal if MR1(7) = 1 and OPR(4) = 1.
IOPCRb[7:6]
IOPCRc[7:6]
IOPCRd[7:6]
Type
I/O3B
I/O3C
I/O3D
3
IPR(6), RxC in
OPRab(6)
RTSN
RxC 1x
RxC 16x
IPR(4), RxC in
OPRcd(4)
RTSN
RxC 1x
RxC 16x
IPR(6), RxC in
OPRcd(6)
RTSN
RxC 1x
RxC 16x
Chan #
2
1
1
1
if IOPCR[5:4] = 01
if IOPCR[5:4] = 01
if IOPCR[5:4] = 01
IOPCRb[5:4]
IOPCRc[5:4]
IOPCRd[5:4]
00, then I/O1 becomes available to the transmitter as an external clock.
I/O2B
I/O2C
I/O2D
20
indicates its source within the UART. The Type field is encoded as
follows:
000
001
x10
011
100
101
111
With Type = x11, the # Bytes field indicates the count of received
bytes available for reading, while with Type = x10 it indicates the
number of bytes that can be written to the transmit FIFO.
The CIR is Read only at address 28H.
IPR(3), TxC in
OPRab(3)
RTSN
C/T ab out
RxC 1x
IPR(1), C/Tcd Clk in
OPRab(1)
RTSN
RxC 16x
RxC 1x
IPR(3), TxC in
OPRcd(3)
RTSN
C/T cd out
RxC 1x
No Interrupt
Change of State
Transmit available
Receive available, no error
Receiver break change
Counter/Timer
Receive available, w/errors
2
2
2
if IOPCR[5:4]
if IOPCR[5:4]
if IOPCR[5:4]
IOPCRb[3:2]
IOPCRd[3:2]
IOPCRc[3:2]
I/O1B
I/O1C
I/O1D
1
TxC in
01
01
01
IPR(2), CTSN
OPRab(2)
TxC 1x
TxC 16x
IPR(0), CTSN
OPRcd(0)
TxC 1x
TxC 16x
IPR(2), CTSN
OPRcd(2)
TxC 1x
TxC 16x
IOPCRb[1:0]
IOPCRc[1:0]
IOPCRd[1:0]
Product specification
SC26C94
I/O0B
I/O0C
I/O0D