scc2681 NXP Semiconductors, scc2681 Datasheet - Page 10

• Manufacturer Part Number: scc2681
• Description: Dual Asynchronous Receiver/transmitter Duart
• Manufacturer: NXP Semiconductors

Philips Semiconductors
shift register is lost and the overrun error status bit (SR[4] will be
set-upon receipt of the start bit of the new (overrunning) character).
The receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated (set to ‘1’)
when a valid start bit was received and the FIFO is full. When a
FIFO position becomes available, the RTSN output will be
re-asserted (set to ‘0’) automatically. This feature can be used to
prevent an overrun, in the receiver, by connecting the RTSN output
to the CTSN input of the transmitting device.
Receiver Reset and Disable
Receiver disable stops the receiver immediately – data being
assembled if the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected.
A receiver reset will discard the present shift register data, reset the
receiver ready bit (RxRDY), clear the status of the byte at the top of
the FIFO and re-align the FIFO read/write pointers. This has the
appearance of “clearing or flushing” the receiver FIFO. In fact, the
FIFO is NEVER cleared! The data in the FIFO remains valid until
overwritten by another received character. Because of this,
erroneous reading or extra reads of the receiver FIFO will miss-align
the FIFO pointers and result in the reading of previously read data.
A receiver reset will re-align the pointers.
Multidrop Mode
Note: Please see Application Note AN10251 for more information
on this feature.
The DUART is equipped with a wake up mode for multidrop
applications. This mode is selected by programming bits MR1A[4:3]
2004 Apr 06
Dual asynchronous receiver/transmitter (DUART)
10
or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this mode
the received data stream and ‘wake up’ the CPU (by setting RxRDY)
programmed number of stop bits. The polarity of the transmitted A/D
should program the mode register prior to loading the corresponding
break detect operate normally whether or not the receive is enabled.
of operation, a ‘master’ station transmits an address character
followed by data characters for the addressed ‘slave’ station. The
slave stations, with receivers that are normally disabled, examine
only upon receipt of an address character. The CPU compares the
received address to its station address and enables the receiver if it
wishes to receive the subsequent data characters. Upon receipt of
another address character, the CPU may disable the receiver to
initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, and Address/Data (A/D) bit, and the
bit is selected by the CPU by programming bit MR1A[2]/MR1B[2].
MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which
identifies the corresponding data bits as data while
MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position, which
identifies the corresponding data bits as an address. The CPU
data bits into the THR.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RHR FIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RHR. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
SCC2681
Product data