isl6341a Intersil Corporation, isl6341a Datasheet - Page 13

• Manufacturer Part Number: isl6341a
• Description: 5v Or 12v Single Synchronous Buck Pulse-width Modulation Pwm Controller
• Manufacturer: Intersil Corporation

The compensation network consists of the error amplifier
(internal to the ISL6341, ISL6341A, ISL6341B) and the external
R
network is to provide a closed loop transfer function with high
0dB crossing frequency (F
adequate phase margin (better than 45°). Phase margin is the
difference between the closed loop phase at F
The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R
and C
the poles and zeros of the compensation network:
4. Select a value for R
5. Calculate C
FIGURE 13. VOLTAGE-MODE BUCK CONVERTER
1
ISL6341, ISL6341A, ISL6341B
to R
value for R
setting the output voltage via an offset resistor connected
to the FB pin (R
be followed as presented.
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
R
C
CIRCUIT
2
3
1
PWM
) in Figure 13. Use the following guidelines for locating
3
=
, C
=
-------------------------------------------- -
d
---------------------------------------------- -
2π R
V
MAX
1
COMP
OSC
to C
COMPENSATION DESIGN
⋅
2
1
⋅
2
V
such that F
HALF-BRIDGE
for desired converter bandwidth (F
3
⋅
OSCILLATOR
⋅
R
IN
1
V
components. The goal of the compensation
0.5 F
o
1
OSC
E/A
DRIVE
⋅
⋅
LC
in Figure 13), the design procedure can
F
F
⋅
R2
LC
1
0
(to adjust, change the 0.5 factor to
LC
(1kΩ to 5kΩ, typically). Calculate the
0
C2
+
-
; typically 0.1 to 0.3 of f
VREF
Z1
C1
13
is placed at a fraction of the F
FB
UGATE
LGATE
PHASE
EXTERNAL CIRCUIT
CE
/F
R3
Ro
LC
V
IN
1
R1
, the lower the F
, R
LC
ISL6341, ISL6341A, ISL6341B
0dB
C3
L
).
2
, R
SW
and 180°.
3
V
, C
0
D
) and
OUT
). If
C
E
(EQ. 5)
(EQ. 4)
1
, C
LC
Z1
2
,
,
It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
G
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 14 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log graph of Figure 14 by adding the modulator gain, G
dB), to the feedback compensation gain, G
equivalent to multiplying the modulator transfer function and the
compensation transfer function and then plotting the resulting
gain.
G
G
F
F
6. Calculate C
7. Calculate R
MOD
CL
Z1
Z2
FB
R
such that F
times f
Change the numerical factor to reflect desired placement
of this pole. Placement of F
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
f ( )
C
f ( )
3
=
=
2
f ( )
=
----------------------------- -
2π
----------------------------------------------- -
2π
=
=
=
------------------- -
---------- - 1
F
=
f
⋅
G
SW
-------------------------------------------------- - ⋅
s f ( )
------------------------------------------------------- -
2π R
⋅
⋅
SW
----------------------------------------------------------------------------------------------------------------------- -
(
LC
1
R
(
MOD
R
d
----------------------------- -
1
1
R
2
MAX
+
⋅
1
+
1
–
). f
V
⋅
⋅
P2
s f ( )
s f ( )
2
R
1
+
3
C
OSC
2
f ( ) G
1
SW
1
such that F
R
such that F
⋅
FB
⋅
is placed below f
⋅
3
C
V
C
⋅
⋅
⋅
(
)
R
1
R
C
) and closed-loop response (G
IN
1
1
represents the switching frequency.
⋅
3
2
1
⋅
FB
C
+
F
⋅
⋅
P2
⋅
+
3
----------------------------------------------------------------------------------------
1
CE
C
s f ( )
C
f ( )
F
C
3
+
1
P1
2
against the capabilities of the error
)
–
s f ( )
)
⋅
P1
Z2
⋅
1
⎛
⎜
⎝
(
=
C
1
R
F
is placed at F
is placed at F
⋅
3
1
+
------------------------------------------- -
2π
P2
P2
(
1
CL
E
+
s f ( )
=
where s f ( )
SW
+
⋅
R
+
=
lower in frequency helps
R
, is constructed on the log-
---------------------------------------------- -
2π R
3
s f ( ) E C
D
2
⋅
----------------------------- -
2π
)
R
) C
(typically, 0.5 to 1.0
⋅
⋅
⋅
1
2
⋅
C
------------------- -
C
C
⋅
⋅
,
3
1
MOD
⋅
3
1
R
1
⎛
⎜
⎝
FB
+
+
3
⋅
⋅
⋅
------------------- -
C
1
C
0.7 f
C
CE
LC
⋅
s
C
1
1
2
C
2
(in dB). This is
2
), feedback
=
+
⋅
f ( ) L C
3
. Calculate C
.
⋅
C
C
2π f j
2
SW
2
⋅
⎞
⎟
⎠
August 20, 2007
⋅ ⋅
⎞
⎟
⎠
CL
⋅
MOD
):
(EQ. 9)
FN6538.0
(EQ. 6)
(EQ. 7)
(EQ. 8)
(in
3