isl6341a Intersil Corporation, isl6341a Datasheet - Page 6

• Manufacturer Part Number: isl6341a
• Description: 5v Or 12v Single Synchronous Buck Pulse-width Modulation Pwm Controller
• Manufacturer: Intersil Corporation

LGATE/OCSET (Pin 4)
Connect this pin to the gate of the lower MOSFET; it provides
the PWM-controlled gate drive (from V
monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
During a short period of time following Power-On Reset
(POR) or shut-down release, this pin is also used to
determine the overcurrent threshold of the converter.
Connect a resistor (R
“Overcurrent Protection (OCP)” on page 7 for equations. An
overcurrent trip latches off the output, requiring cycling V
off and on, or by toggling COMP/EN. Some of the text
describing the LGATE function may leave off the OCSET
part of the name when it is not relevant to the discussion.
PGOOD (Pin 10)
This output is an open-drain pull-down device that reflects
the state of the PGOOD comparators. An external pull-up
resistor should be connected to a supply ≤6V. The output will
be held low through the soft-start ramp, and is allowed to go
high at the end of soft-start, if the VOS voltage is within its
window. The PGOOD window is tighter than the OV or UV
protection window, so it may give an early warning of a
problem. The PGOOD does respond directly to an OCP
condition, but may also go low if V
before an OCP trip.
Functional Description
Initialization (POR and OCP sampling)
Figure 1 shows a simplified timing diagram. The Power-On-
Reset (POR) function continually monitors the bias voltage
at the VCC pin. Once the rising POR threshold is exceeded
(V
Overcurrent Protection (OCP) sample and hold operation
(while COMP/EN is ~1V). When the sampling is complete,
V
If the COMP/EN pin is held low during power-up, that will just
delay the initialization until it is released and the COMP/EN
voltage is above the V
ISL6341
ISL6341A 600kHz
ISL6341B 600kHz
NUMBER
OUT
POR
PART
TABLE 1. SUMMARY OF FEATURE DIFFERENCES
begins the soft-start ramp.
= 4.3V nominal), the POR function initiates the
300kHz
f
SW
CYCLE
DUTY
MAX
75%
85%
75%
OCSET
ENABLE
“Hiccup” mode (infinite retries)
Latch off; toggle POR or COMP/EN
to restart
Latch off; toggle POR or COMP/EN
to restart
) from this pin to GND. See
(OVERCURRENT PROTECTION)
6
trip point.
OUT
CC
drops low enough
). This pin is also
OCP
ISL6341, ISL6341A, ISL6341B
CC
Figure 2 shows a typical power-up sequence in more detail.
The initialization starts at t0, when either V
V
COMP/EN will be pulled up by an internal 20µA current
source, but the timing will not begin until the COMP/EN
exceeds the V
capacitance of the disabling device, as well as the
compensation capacitors, will determine how quickly the
20µA current source will charge the COMP/EN pin. With
typical values, it should add a small delay compared to the
soft-start times. The COMP/EN will continue to ramp to ~1V.
From t1, there is a nominal 4ms delay, which allows the VCC
pin to rise. At the same time, the LGATE/OCSET pin is
initialized by disabling the LGATE driver and drawing I
(nominal 10μA) through R
will represent the OCSET trip point for the OCP sample and
hold operation. The sample and hold uses a digital counter and
DAC (to save the voltage so the stored value does not degrade)
for as long as the V
Protection (OCP)” on page 7 for more details on the equations
and variables. Upon the completion of sample and hold at t2,
the soft-start operation is initiated (around 0.8ms delay to t3),
GND>
GND>
GND>
GND>
GND>
GND>
GND>
GND>
POR
FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION
, or the COMP/EN pin is released (after POR). The
FIGURE 1. POR AND SOFT-START OPERATION
t0
0.7V
ENABLE
t1
LGATE/OCSET
CC
~4.3V POR
COMP/EN (0.25V/DIV)
4.0ms
0.25V/DIV
is above V
trip point (at t1). The external
OCSET
t2
0.8ms
COMP/EN (1V/DIV)
. This sets up a voltage that
t3
POR
. See “Overcurrent
SWITCHING
4.0ms
STARTS
LGATE
CC
PGOOD (2V/DIV)
rises above
t4
V
V
OUT
CC
(0.25V/DIV)
August 20, 2007
V
(2V/DIV)
(1V/DIV)
OUT
OCSET
FN6538.0