isl6237 Intersil Corporation, isl6237 Datasheet
isl6237
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isl6237 Summary of contents
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... PART RANGE NUMBER MARKING (° C) ISL6237IRZ ISL6237 IRZ -40 to +100 32 Ld 5x5 QFN L32.5x5B (Note) ISL6237IRZ-T ISL6237 IRZ -40 to +100 32 Ld 5x5 QFN (Note) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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... Pinout EN_LDO LDOREFIN 2 ISL6237 ISL6237 (32 LD 5x5 QFN) TOP VIEW REF 1 TON 2 VCC VIN 6 LDO BOOT2 LGATE2 23 22 PGND GND PVCC 19 LGATE1 18 BOOT1 17 16 FN6418.1 March 16, 2007 ...
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... REFIN2) DC Load Regulation Line Regulation Current-Limit Current Source ILIM_ Adjustment Range Current-Limit Threshold (Positive, Default) 3 ISL6237 Thermal Information Thermal Resistance (Typical QFN (Notes Operating Temperature Range . . . . . . . . . . . . . . . .-40°C to +10 0°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +15 0°C ...
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... LDOREFIN Input Range LDO Output Current LDO Output Current During Switchover LDO Output Current During Switchover to 3.3V LDO Short-Circuit Current 4 ISL6237 = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V 5V -40° +100° C, unless otherwise noted. Typical values are CONDITIONS GND - PHASE_ ...
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... Output Undervoltage Shutdown Blanking Time INPUTS AND OUTPUTS FB1 Input Voltage REFIN2 Input Voltage LDOREFIN Input Voltage 5 ISL6237 = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V 5V -40° +100° C, unless otherwise noted. Typical values are CONDITIONS Rising edge of PVCC ...
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... LGATE_ Gate-Driver Source Current LGATE_ Gate-Driver Sink Current UGATE_ Gate-Driver On-Resistance LGATE_ Gate-Driver On-Resistance Dead Time OUT1, OUT2 Discharge On Resistance 6 ISL6237 = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V 5V -40° +100° C, unless otherwise noted. Typical values are CONDITIONS ...
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... Analog Ground for both SMPS_ and LDO. Connect externally to the underside of the exposed pad. 21 PGND Power Ground for SMPS_ controller. Connect PGND externally to the underside of the exposed pad. 22 LGATE2 SMPS2 Synchronous-Rectifier Gate-Drive Output. LGATE2 swings between GND and PVCC ISL6237 FUNCTION FN6418.1 March 16, 2007 ...
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... OUTPUT LOAD (A) FIGURE 1.05V EFFICIENCY vs LOAD (300kHz) OUT2 8 ISL6237 FUNCTION Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, V EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V otherwise noted. Typical values are at T ULTRA SKIP MODE IN SKIP MODE ...
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... OUTPUT LOAD (A) FIGURE 3.3V REGULATION vs LOAD (500kHz) OUT2 9 ISL6237 Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, V EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V otherwise noted. Typical values are at T ULTRA SKIP MODE IN SKIP MODE IN PWM MODE ...
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... INPUT VOLTAGE (V) FIGURE 13 1.05V OUTPUT VOLTAGE REGULATION OUT2 vs V (PWM MODE ISL6237 Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, V EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V otherwise noted. Typical values are at T ULTRA SKIP MODE IN SKIP MODE IN ...
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... INPUT VOLTAGE (V) FIGURE 19 OUTPUT VOLTAGE REGULATION vs OUT1 V (PWM MODE ISL6237 Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, V EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V otherwise noted. Typical values are at T 1.530 1.525 1.520 MID LOAD PWM 1 ...
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... ULTRA-SKIP 100 SKIP 0 0.001 0.010 0.100 OUTPUT LOAD (A) FIGURE 25 3.3V FREQUENCY vs LOAD OUT2 12 ISL6237 Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, V EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V otherwise noted. Typical values are ...
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... INPUT VOLTAGE (V) FIGURE 31. PWM NO LOAD INPUT CURRENT vs V (EN = EN2 = EN_LDO = VCC) 13 ISL6237 Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, V EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V otherwise noted. Typical values are ...
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... EN2 = 0, EN_LDO = VCC) FIGURE 35. START-UP V EN1 5V/DIV V 2V/DIV OUT1 IL1 2A/DIV POK1 2V/DIV FIGURE 36. START- (NO LOAD, PWM MODE) OUT1 14 ISL6237 Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, V EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V otherwise noted. Typical values are at T 26.5 26.0 25.5 25.0 24.5 24.0 23.5 23.0 22 ...
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... OUT2 POK1 5V/DIV POK2 5V/DIV FIGURE 42. DELAYED START-UP (V OUT1 EN2 = REF) 15 ISL6237 Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, V EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V otherwise noted. Typical values are at T POK2 2V/DIV FIGURE 39. START-UP V EN2 5V/DIV ...
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... OUT LDO 1V/DIV LDOREFIN 0.5V/DIV V RIPPLE 50mV/DIV OUT2 FIGURE 48. LDO TRACKING TO LDOREFIN 16 ISL6237 Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, V EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V otherwise noted. Typical values are FIGURE 45. LOAD TRANSIENT V OUT1 = 3.3V (PWM) FIGURE 47 ...
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... IL2 2A/DIV POK2 2V/DIV FIGURE 54. START- 1.05V (FULL LOAD, OUT1 PWM MODE) 17 ISL6237 Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, V EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V otherwise noted. Typical values are at T POK1 2V/DIV FIGURE 51. START-UP V POK2 2V/DIV FIGURE 53 ...
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... RIPPLE 20mV/DIV OUT1 IL1 5A/DIV V RIPPLE 20mV/DIV OUT2 FIGURE 60. LOAD TRANSIENT V OUT1 18 ISL6237 Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, V EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V otherwise noted. Typical values are OUT1 = 1.5V, FIGURE 57. SHUTDOWN (V = 1.5V (PWM) FIGURE 59. LOAD TRANSIENT ...
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... PWM comparator, high-side and low-side gate drivers and logic. In addition, SMPS2 can also use REFIN2 to track its output from 0.5V to 2.5V. The ISL6237 contains fault- protection circuits that monitor the main PWM outputs for undervoltage and overvoltage conditions. A power-on sequence block controls the power-up timing of the main PWMs and monitors the outputs for undervoltage faults ...
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... DROP2 3.3 ±10 charging path, including high-side switch, inductor, and PC board resistances • OUT DROP1 DROP2 is the sum of the parasitic voltage drops in the is the sum of the parasitic voltage drops in the is the on-time calculated by the ISL6237 (EQ. 2) FN6418.1 March 16, 2007 ...
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... R1 VCC 7.87k: 5V FB1 TIED TO GND = 5V FB1 TIED TO VCC = 1. 200k: 10k: VCC FIGURE 62. ISL6237 TYPICAL GFX APPLICATION CIRCUIT 21 ISL6237 1µF PVCC VCC LDO VIN LDOREFIN BOOT1 BOOT2 UGATE2 UGATE1 PHASE2 PHASE1 LGATE2 LGATE1 ...
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... FB1 TIED TO VCC = 1. 200k OFF OFF OFF VCC FREQUENCY-DEPENDENT COMPONENTS 1.5V/1.05V SMPS FIGURE 63. ISL6237 TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT 22 ISL6237 1µF PVCC VCC LDO VCC VIN LDOREFIN BOOT1 BOOT2 UGATE2 UGATE1 C 4 0.22µF ...
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... EN1 FB1 POK1 OUT1 OUT1 BYP SW THRES. LDO LDO LDOREFIN VIN EN_LDO POWER-ON SEQUENCE EN1 CLEAR FAULT LATCH EN2 FIGURE 64. DETAIL FUNCTIONAL DIAGRAM ISL6237 23 ISL6237 TON SKIP# SMPS2 SYNCH. PWM BUCK CONTROLLER EN2 POK2 OUT2 INTERNAL LOGIC REF THERMAL THERMAL SHUTDOWN ...
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... REFIN2 (SMPS2 VREF + ILIM_ + COMP SLOPE COMP + + + 5µA VCC + + PHASE_ OUT_ FB DECODER 0.9V REF FB_ 1.1V REF 0.7V REF FIGURE 65. PWM CONTROLLER (ONE SIDE ONLY) 24 ISL6237 MIN. t OFF Q TRIG ONE SHOT TO UGATE_DRIVER BOOT UV DETECT TO LGATE_ DRIVER ...
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... The load-current level at which ON) PFM/PWM crossover occurs, I LOAD(SKIP) the peak-to-peak ripple current, which is a function of the inductor value (Figure 66). For example, in the ISL6237 typical application circuit with V OUT1 L = 7.6µH, and K = 5µs, switchover to pulse-skipping operation occurs 0.96A or about on-fifth full load. ...
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... ILIM_ is adjusted. The current-limit threshold is adjusted with an external resistor for ISL6237 at ILIM_. The current-limit threshold adjustment range is from 20mV to 200mV. In the adjustable mode, the current-limit threshold voltage is 1/10th the voltage at ILIM_. The voltage at ILIM pin is the product of 5µ ...
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... If the voltage falls too low, the converter may not be able to turn on UGATE when the output voltage falls to the reference. To prevent this, the ISL6237 monitors the BOOT capacitor voltage, and if it falls below 3V, it initiates an LGATE pulse, which will refresh the BOOT voltage. ...
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... Shutdown Mode The ISL6237 SMPS1, SMPS2 and LDO have independent enabling control. Drive EN1, EN2 and EN_LDO below the precise input falling-edge trip level to place the ISL6237 in its low-power shutdown state. The ISL6237 consumes only 20µA of quiescent current while in shutdown. Both SMPS outputs are discharged to 0V through a 25: switch ...
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... Inductor values lower than this grant no further size-reduction benefit. The ISL6237 pulse-skipping algorithm (SKIP# = GND) initiates skip mode at the critical conduction point, so the inductor's operating point also determines the load (EQ ...
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... IN where minimum off-time = 0.35µs (max) and K is from Table 2. 30 ISL6237 Determining the Current Limit The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor ...
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... The input capacitors must meet the input-ripple-current (I ) requirement imposed by the switching current. The RMS ISL6237 dual switching regulator operates at different frequencies. This interleaves the current pulses drawn by the two switches and reduces the overlap time where they add together. The input RMS current is much smaller in comparison than with both SMPSs operating in phase ...
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... This is especially true when multiple converters are on the same PC board where one circuit can affect the other. Refer to the ISL6237 Evaluation Kit data sheet for a specific layout example. Mount all of the power components on the top side of the board with their ground terminals flush against one another, if possible ...
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... MOSFET, input, and output capacitors) to the small island with a single short, wide connection (preferably just a via). Create PGND islands on the layer just below the top-side layer (refer to the ISL6237 EV kit for an example) to act as an EMI shield if multiple layers are available (highly recommended). Connect each of these individually to the star ground via, which connects the top side to the PGND plane ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 34 ISL6237 L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...