isl6237 Intersil Corporation, isl6237 Datasheet - Page 19

• Manufacturer Part Number: isl6237
• Description: High-efficiency, Quad-output, Main Power Supply Controllers For Notebook Computers
• Manufacturer: Intersil Corporation

Typical Application Circuits
The typical application circuits (Figures 62 and 63) generate the
typical 5V/7A, 3.3V/11A, 1.25V/5A, static voltage/10A, 1.5V/5A,
and 1.05V/5A supplies found in a notebook computer. The
input supply range is 5.5V to 25V.
Detailed Description
The ISL6237 dual-buck, BiCMOS, switch-mode power-
supply controller generates logic supply voltages for
notebook computers. The ISL6237 is designed primarily for
battery-powered applications where high efficiency and low-
quiescent supply current are critical. The ISL6237 provides a
pin-selectable switching frequency, allowing operation for
200kHz/300kHz, 400kHz/300kHz, or 400kHz/500kHz on the
SMPSs.
Light-load efficiency is enhanced by automatic Idle-Mode
operation, a variable-frequency pulse-skipping mode that
reduces transition and gate-charge losses. Each step-down,
power-switching circuit consists of two N-Channel
MOSFETs, a rectifier, and an LC output filter. The output
voltage is the average AC voltage at the switching node,
which is regulated by changing the duty cycle of the
MOSFET switches. The gate-drive signal to the N-Channel
high-side MOSFET must exceed the battery voltage, and is
provided by a flying-capacitor boost circuit that uses a 100nF
capacitor connected to BOOT_.
Both SMPS1 and SMPS2 PWM controllers consist of a
triple-mode feedback network and multiplexer, a multi-input
PWM comparator, high-side and low-side gate drivers and
logic. In addition, SMPS2 can also use REFIN2 to track its
output from 0.5V to 2.5V. The ISL6237 contains fault-
protection circuits that monitor the main PWM outputs for
undervoltage and overvoltage conditions. A power-on
sequence block controls the power-up timing of the main
PWMs and monitors the outputs for undervoltage faults. The
ISL6237 includes an adjustable low drop-out linear regulator.
The bias generator blocks include the linear regulator, a 2V
precision reference and automatic bootstrap switchover
circuit.
The synchronous-switch gate drivers are directly powered
from PVCC, while the high-side switch gate drivers are
indirectly powered from PVCC through an external capacitor
and an internal Schottky diode boost circuit.
An automatic bootstrap circuit turns off the LDO linear
regulator and powers the device from BYP if LDOREFIN is
set to GND or VCC. See Table 1.
VOLTAGE at BYP
VOLTAGE at BYP
LDO VOLTAGE
TABLE 1. LDO OUTPUT VOLTAGE TABLE
LDOREFIN < 0.3V,
BYP > 4.63V
LDOREFIN > VCC - 1V,
BYP > 3V
CONDITIONS
19
Internal LDO is
disabled.
Internal LDO is
disabled.
COMMENT
ISL6237
FREE-RUNNING, CONSTANT ON-TIME PWM
CONTROLLER WITH INPUT FEED-FORWARD
The constant on-time PWM control architecture is a
pseudo-fixed-frequency, constant on-time, current-mode
type with voltage feed forward. The constant on-time PWM
control architecture relies on the output ripple voltage to
provide the PWM ramp signal; thus the output filter
capacitor's ESR acts as a current-feedback resistor. The
high-side switch on-time is determined by a one-shot whose
period is inversely proportional to input voltage and directly
proportional to output voltage. Another one-shot sets a
minimum off-time (300ns typ). The on-time one-shot triggers
when the following conditions are met: the error comparator's
output is high, the synchronous rectifier current is below the
current-limit threshold, and the minimum off time one-shot
has timed out. The controller utilizes the valley point of the
output ripple to regulate and determine the off time.
On-Time One-Shot (t
Each PWM core includes a one-shot that sets the high-side
switch on-time for each controller. Each fast, low-jitter,
adjustable one-shot includes circuitry that varies the on-time
in response to battery and output voltage. The high-side
switch on-time is inversely proportional to the battery voltage
as measured by the VIN input and proportional to the output
voltage. This algorithm results in a nearly constant switching
frequency despite the lack of a fixed-frequency clock
generator. The benefit of a constant switching frequency is
that the frequency can be selected to avoid noise-sensitive
frequency regions:
See Table 2 for approximate K- factors. Switching frequency
increases as a function of load current due to the increasing
drop across the synchronous rectifier, which causes a faster
inductor-current discharge ramp. On-times translate only
roughly to switching frequencies. The on-times guaranteed in
the Electrical Characteristics are influenced by switching
delays in the external high-side power MOSFET. Also, the
dead-time effect increases the effective on-time, reducing the
switching frequency. It occurs only in PWM mode (SKIP# =
VCC) and during dynamic output voltage transitions when the
inductor current reverses at light or negative load currents.
With reversed inductor current, the inductor's EMF causes
PHASE to go high earlier than normal, extending the on-time
by a period equal to the UGATE-rising dead time.
5V
3.3V
2 x LDOREFIN
t
ON
LDO VOLTAGE
TABLE 1. LDO OUTPUT VOLTAGE TABLE (Continued)
=
K V
----------------------------------------------------------------------------------------------------- -
OUT
+
I
LOAD
LDOREFIN < 0.3V,
BYP < 4.63V
LDOREFIN > VCC - 1V,
BYP < 3V
0.35V < LDOREFIN < 2.25V
ON
V
˜
IN
r
)
DSON LOWERQ
CONDITIONS
Internal LDO is
active.
Internal LDO is
active.
Internal LDO is
active.
COMMENT
March 16, 2007
(EQ. 1)
FN6418.1