ds3104 Maxim Integrated Products, Inc., ds3104 Datasheet
ds3104
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ds3104 Summary of contents
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... Rev: 012108 General Description The DS3104- low-cost, feature-rich timing IC for line cards with Synchronous Gigabit Ethernet (GbE), 10-Gigabit Ethernet (10GbE), and Fast Ethernet ports. ITU-T recommendation G.8261 (formerly G.pactiming) specifies that network synchronization can be carried over packet links by synchronizing the bit clock of the physical layer as is currently done on SONET/SDH links ...
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... DS3104-SE 1. STANDARDS COMPLIANCE ..........................................................................................................6 2. APPLICATION EXAMPLE ...............................................................................................................7 3. BLOCK DIAGRAM ...........................................................................................................................8 4. DETAILED DESCRIPTION ..............................................................................................................9 5. DETAILED FEATURES .................................................................................................................11 5 NPUT LOCK EATURES 5 IMING ARD TO INE ARD 5 INE ARD TO IMING ARD 5.4 O APLL F UTPUT EATURES 5 UTPUT LOCK EATURES 5 .....................................................................................................................12 ...
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... DS3104-SE 7.9.2 Resampling .......................................................................................................................................... 46 7.9.3 Qualification ......................................................................................................................................... 46 7.9.4 Output Clock Alignment ....................................................................................................................... 46 7.9.5 Frame-Sync Monitor............................................................................................................................. 47 7.9.6 SYNCn Pins ......................................................................................................................................... 47 7.9.7 Other Configuration Options ................................................................................................................ 48 7. ICROPROCESSOR NTERFACE 7. .............................................................................................................................51 ESET OGIC 7. OWER UPPLY ONSIDERATIONS 7.13 I ............................................................................................................................51 NITIALIZATION 8. REGISTER DESCRIPTIONS .........................................................................................................52 8 .................................................................................................................................52 TATUS ITS 8 ONFIGURATION IELDS 8 .................................................................................................................52 ULTIREGISTER IELDS 8 .................................................................................................................53 EGISTER EFINITIONS 9 ...
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... DS3104-SE Figure 2-1. Typical Application Example ..................................................................................................................... 7 Figure 3-1. Block Diagram ........................................................................................................................................... 8 Figure 7-1. DPLL Block Diagram ............................................................................................................................... 25 Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 27 Figure 7-3. T4 DPLL State Transition Diagram ......................................................................................................... 30 Figure 7-4. FSYNC 8kHz Options.............................................................................................................................. 44 Figure 7-5. SPI Clock Phase Options ........................................................................................................................ 49 Figure 7-6. SPI Bus Transactions.............................................................................................................................. 50 Figure 9-1. JTAG Block Diagram............................................................................................................................. 117 Figure 9-2 ...
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... DS3104-SE Table 1-1. Applicable Telecom Standards................................................................................................................... 6 Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 13 Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 14 Table 6-3. Global Pin Descriptions ............................................................................................................................ 15 Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 15 Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 16 Table 6-6. Power-Supply Pin Descriptions ................................................................................................................ 16 Table 7-1. Input Clock Capabilities ............................................................................................................................ 19 Table 7-2. Locking Frequency Modes ....................................................................................................................... 20 Table 7-3 ...
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... DS3104-SE 1. Standards Compliance Table 1-1. Applicable Telecom Standards SPECIFICATION ANSI T1.101 Synchronization Interface Standard, 1999 TIA/EIA-644-A Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, 2001 ETSI Transmission and Multiplexing (TM); Generic requirements of transport functionality of EN 300 417-6-1 equipment; Part 6-1: Synchronization layer functions, v1.1.3 (1999-05) Transmission and Multiplexing (TM) ...
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... DS3104-SE 2. Application Example Figure 2-1. Typical Application Example 4-Port Gigabit Ethernet Line Card Synchronization clock flow only. 10-Gigabit and Fast Ethernet ports and SONET/SDH ports also supported. TX GMII GigE to GigE optical RX GMII PHY components TX GMII GigE to GigE optical RX GMII PHY components ...
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... DS3104-SE 3. Block Diagram Figure 3-1. Block Diagram IC1 POS/NEG IC2 POS/NEG IC3 IC4 IC5 POS/NEG IC6 POS/NEG IC8 IC9 SYNC1 SYNC2 SYNC3 JTRST JTMS JTAG JTCLK JTDI JTDO Rev: 012108 T4 DPLL (Frequency Conversion) Input PLL Bypass Synthesizer Clock Selector, Divider and ...
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... Although strictly speaking these names are appropriate only for timing card ICs such as the DS3100 that can serve as the SETS function, the names have been carried over to the DS3104-SE so that all of the products in Maxim’s timing IC product line have consistent nomenclature. ...
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... The entire chip is clocked from the external oscillator connected to the REFCLK pin. Thus, the free-run and holdover stability of the DS3104-SE is entirely a function of the stability of the external oscillator, the performance of which can be selected to match the application TCXO. The 12.8MHz clock from the external oscillator is multiplied the Master Clock Generator block to create the 204 ...
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... DS3104-SE 5. Detailed Features 5.1 Input Clock Features • Eight input clocks: four CMOS/TTL (≤ 125MHz) and four LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz) • CMOS/TTL input clocks accept any multiple of 2kHz up to 125MHz • LVDS/LVPECL inputs accept any multiple of 2kHz up to 131.072MHz, any multiple of 8kHz up to 155.52MHz plus 156.25MHz • ...
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... DS3104-SE 5.4 Output APLL Features • Three separate clock-multiplying, jitter attenuating APLLs can simultaneously produce SONET/SDH rates, Fast/Gigabit Ethernet rates and 10G Ethernet rates, all locked to a common reference clock • The T0 APLL, always connected to the T0 DPLL, has frequency options suitable for N x 19.44MHz DS1 E1 25MHz, and N x 62.5MHz • ...
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... DS3104-SE 6. Pin Descriptions Table 6-1. Input Clock Pin Descriptions (1) (2) PIN NAME TYPE Reference Clock. Connect to a 12.800MHz, high-accuracy, high-stability, low-noise local REFCLK I oscillator (XO or TCXO). See Section 7.3. Input Clock 1. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 8kHz). IC1POS, I LVDS/LVPECL: See DIFF IC1NEG CMOS/TTL: Bias IC1NEG to 1 ...
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... DS3104-SE Table 6-2. Output Clock Pin Descriptions (1) (2) PIN NAME TYPE OC1 O Output Clock 1. CMOS/TTL. Programmable frequency (default 25MHz) OC2 O Output Clock 2. CMOS/TTL. Programmable frequency (default 62.5MHz). OC3 O Output Clock 3. CMOS/TTL. Programmable frequency (default 77.76MHz) OC4 O Output Clock 4. CMOS/TTL. Programmable frequency (default 125MHz) ...
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... DS3104-SE Table 6-3. Global Pin Descriptions (1) (2) PIN NAME TYPE Reset (Active Low). When this global asynchronous reset is pulled low, all internal circuitry is reset to default values. The device is held in reset as long as RST is low. RST should be held RST I PU low for at least two REFCLK cycles after the external oscillator has stabilized and is providing valid clock signals ...
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... DS3104-SE Table 6-5. JTAG Interface Pin Descriptions See Section 9 for functional description and Section (1) (2) PIN NAME TYPE JTAG Test Reset (Active Low). Asynchronously resets the test access port (TAP) controller. If JTRST I PU not used, JTRST can be held low or high. JTAG Clock. Shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If ...
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... Overview The DS3104-SE has eight input clocks pins and three frame-sync input pins. The device can output as many as nine different clock frequencies on 16 output clock pins. There are two separate DPLLs in the device: the high- performance T0 DPLL and the simpler the T4 DPLL. Both DPLLs can generate output clocks. See Four of the input clock pins are single-ended and can accept clock signals from 2kHz to 125MHz ...
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... The MCLKFREQ field in registers be applied. The adjust can be from -771ppm to +514ppm in 0.0196229ppm (i.e., ~0.02ppm) steps. The DS3104-SE has a watchdog circuit that causes an interrupt on the INTREQ pin when the local oscillator attached to the REFCLK pin is significantly off frequency. The watchdog interrupt is not maskable, but is subject to ...
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... Input Clock Configuration The DS3104-SE has eight input clocks: IC1 to IC6, IC8, and IC9. each clock, including signal format and available frequencies. The device tolerates a wide range of duty cycles on input clocks, out to a minimum high time or minimum low time of 3ns or 30% of the clock period, whichever is smaller ...
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... DS3104-SE 7.4.2 Frequency Configuration Input clock frequencies are configured in the FREQ field of the same registers specify the locking frequency mode, as shown in Table 7-2. Locking Frequency Modes LOCKING FREQUENCY DIVN LOCK8K 0 0 Direct Lock 0 1 LOCK8K 1 0 DIVN 1 1 Alternate Direct Lock 7.4.2.1 Direct Lock Mode In direct lock mode, the DPLLs lock to the selected reference at the frequency specified in the corresponding register ...
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... DPLL does not have any valid input clocks available, the T4NOIN status bit is set MSR3. 7.5.1 Frequency Monitoring The DS3104-SE monitors the frequency of each input clock and invalidates any clock whose frequency is more than 10,000ppm away from nominal. The frequency range monitor can be disabled by clearing the MCR1.FREN bit ...
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... DS3104-SE 7.5.2) is too slow to be suitable for monitoring the selected reference. Instead, each DPLL has its own fast activity monitor that detects that the frequency is within range (approximately 10,000ppm) and detects inactivity within approximately two missing reference clock cycles (approximately four missing cycles for 156.25MHz, 155.52MHz, 125MHz, 62 ...
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... DS3104-SE The reference selection algorithm for each DPLL chooses the highest priority valid input clock to be the selected reference. To select the proper input clock based on these criteria, the selection algorithm maintains a priority table of valid inputs. The top three entries in this table and the selected reference are displayed in the PTAB2 registers ...
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... DS3104-SE in revertive mode, ultra-fast switching could cause excessive reference switching when the highest priority input is intermittent. 7.6.5 External Reference Switching Mode In this mode the SRCSW input pin controls reference switching between two clock inputs. This mode is enabled by setting the EXTSW bit the ...
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... DS3104-SE 7.7 DPLL Architecture and Configuration Both T0 and T4 are digital PLLs with separate analog PLLs (APLLs) as the output stage. This architecture combines the benefits of both PLL types. See Figure 7-1. DPLL Block Diagram selected PFD and Foward reference Loop Filter DFS ...
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... DS3104-SE Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations, temperature, and voltage; and (2) flexible behavior that is easily programmed through the configuration registers. DPLLs use digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock (204 ...
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... DS3104-SE Figure 7-2. T0 DPLL State Transition Diagram (selected reference invalid > 2s [selected reference invalid OR out of lock >100s OR (revertive mode AND valid higher priority input)] AND valid input clock available [selected reference invalid OR (revertive mode AND valid higher priority input)] AND valid input clock available ...
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... DS3104-SE 7.7.1.3 Locked State The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states when the DPLL has locked to the selected reference for at least 2 seconds (see Section 7.7.6). In the locked state the output clocks track the phase and frequency of the selected reference. ...
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... DS3104-SE 7.7.1.6.1 Automatic Holdover For automatic holdover (FRUNHO = 0 in MCR3), the device can be further configured for instantaneous mode or averaged mode. In instantaneous mode (AVG = 0 in HOCR3), the holdover frequency is set to the DPLL’s current frequency 50ms to 100ms before entry into holdover (i.e., the value of the FREQ field in the FREQ1, FREQ2, and FREQ3 registers when MCR11:T4T0 = 0). The FREQ field is the DPLL’ ...
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... DS3104-SE Figure 7-3. T4 DPLL State Transition Diagram SELECTED REFERENCE SWITCH SELECTED REFERENCE PHASE-LOCKED > 2s SELECTED REFERENCE SWITCH PRELOCKED 2 Rev: 012108 RESET FREE-RUN SELECTED REFERENCE SELECTED REFERENCE INACTIVE > 2s ACTIVE PRELOCKED PHASE-LOCKED TO SELECTED REFERENCE > 2s LOCKED LOSS-OF-LOCK ON PHASE-LOCK REGAINED SELECTED REFERENCE ON SELECTED REFERENCE > ...
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... DS3104-SE 7.7.3 Bandwidth The bandwidth of the T4 DPLL is configured in the The bandwidth of the T0 DPLL is configured in the 400Hz. The AUTOBW bit in the MCR9 T0 DPLL uses the T0ABW bandwidth during acquisition (not phase-locked) and the T0LBW bandwidth when phase-locked. When AUTOBW = 0 the T0 DPLL uses the T0LBW bandwidth all the time, both during acquisition and when phase-locked ...
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... DS3104-SE The T0 DPLL phase detectors can be configured for normal phase/frequency locking (±360° capture) or nearest edge phase locking (±180° capture). With nearest edge detection the phase detectors are immune to occasional missing clock cycles. The DPLL automatically switches to nearest edge locking when the multicycle phase detector is disabled and the other phase detectors determine that phase lock has been achieved ...
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... DS3104-SE When the T0 DPLL declares loss-of-lock, the state machine immediately transitions to the loss-of-lock state, which sets the STATE bit in the MSR2 register and requests an interrupt if enabled. When the T4 DPLL declares loss-of-lock, the T4LOCK bit is cleared in the T4LOCK bit in the MSR3 register and requests an interrupt if enabled ...
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... DS3104-SE During the recalibration process the device puts the DPLL into mini-holdover, internally ramps the phase offset to zero, resets all clock dividers, ramps the phase offset to the value stored in the the DPLL out of mini-holdover. If the ramps the phase offset to the new offset value. ...
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... DS3104-SE Table 7-5. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode LOCKING MODE LOCKING FOR T4 MODE FOR T0 SELECTED SELECTED REFERENCE REFERENCE LOCK8K or DIRECT DIVN(8K) LOCK8K or LOCK8K DIVN(8K) LOCK8K or DIVN (8K) DIVN(8K) LOCK8K or DIVN (not 8K) DIVN(8K) DIVN (not 8K) Any DIRECT Any Note 1: In this case, the T0 select reference must be the same frequency as the T4 selected reference. ...
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... DS3104-SE 7.7.13 Output Jitter and Wander Several factors contribute to jitter and wander on the output clocks, including: • Jitter and wander amplitude on the selected reference (while in the locked state) • The jitter/wander transfer characteristic of the device (while in the locked state) • The jitter and wander on the local oscillator clock signal (especially wander while in the holdover state) The DPLL in the device has programmable bandwidth (see Section 7 ...
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... The frequency of output clocks OC1 to OC7 is a function of the settings used to configure the components of the T0 and T4 PLL paths. These components are shown in the detailed block diagram of The DS3104-SE uses digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock (204.8MHz) is divided down to the desired output frequency by adding a number to an accumulator. The DFS output is a coding of the clock output phase that is used by a special circuit to determine where to put the edges of the output clock between the clock edges of the master clock ...
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... DS3104-SE 7.8.2.1 T0 and T4 DPLL Details See Figure 7-1. The T0 and T4 forward-DFS blocks use the 204.8MHz master clock and DFS technology to synthesize internal clocks from which the output and feedback clocks are derived. The T4 DPLL only has a single DFS output clock signal for both the output clocks and the feedback clock, whereas there are two DFS output clock signals in the T0 DPLL— ...
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... DS3104-SE 7.8.2.3 OC1 to OC7 Configuration The following is a step-by-step procedure for configuring the frequencies of output clocks OC1 to OC7: 1) Determine whether the T4 APLL must be independent of the T0 DPLL. If the T4 APLL must be independent, set T4APT0 = 0 in register T0CR1. If the T4 APLL must be locked to the T0 DPLL, set T4APT0 = 1 ...
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... DS3104-SE Table 7-9. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) APLL APLL / APLL / FREQUENCY 2 4 312.500 156.250 — 311.040 155.520 77.760 274.944 137.472 68.376 250.000 125.000 62.500 178.944 89.472 44.736 160.000 80.000 40.000 148.224 74.112 37.056 131.072 65.536 32.768 30.720 122.880 61 ...
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... DS3104-SE Table 7-12. T4 APLL Frequency Configuration T4 APLL T4 APLL DFS FREQUENCY FREQUENCY (MHz) (MHz) Disabled 77.76 311.04 77.76 98.304 24.576 131.072 32.768 148.224 37.056 98.816 24.704 274.944 68.736 178.944 44.736 100.992 25.248 250.000 62.500 122.88 30.720 160.000 40.000 104.000 26.000 98.304 24.576 250.000 62.500 131 ...
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... DS3104-SE Table 7-14. Standard Frequencies for Programmable Outputs FREQUENCY (MHz) 2kHz 8kHz 1.536 Not OC4, OC5 from T4 APLL Not OC4–OC7 from T0 APLL 1.544 Not OC6 from DIG2 1.544 Not OC4, OC5 from T4 APLL Not OC4–OC7 from T0 APLL 1.578 Not OC4, OC5 from T4 APLL n ot OC4– ...
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... DS3104-SE FREQUENCY (MHz) 16.000 Not OC6, OC7 16.384 Not OC6 from DIG2 16.384 16.384 16.832 17.184 18.528 19.440 Not OC6 19.440 20.000 20.800 OC2, OC3, OC6, OC7 only 22.368 24.576 24.576 OC2, OC3, OC6, OC7 only 24.704 24.704 25.000 Not OC6, OC7 25 ...
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... DS3104-SE FREQUENCY (MHz) 122.880 OC6, OC7 only 125.000 Not OC1–OC3 from T0 APLL Not OC1, OC2 from T4 APLL 131.072 Not OC1–OC3 from T0 APLL OC6, OC7 only from T4 APLL 137.472 OC6, OC7 only 148.224 Not OC1–OC3 from T0 APLL OC6, OC7 only from T4 APLL 155.520 Not OC1– ...
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... The higher speed clock from each timing card is connected to a regular input clock pin on the DS3104-SE, such as IC3 or IC4, while the frame-sync signal is connected to a SYNCn input pin on the DS3104-SE, such as SYNC1 or SYNC2. The DS3104-SE locks to the higher speed clock from one of the timing cards and samples the frame-sync signal on the associated SYNCn pin ...
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... DS3104-SE Table 7-15. External Frame-Sync Mode and Source T0 DPLL MCR3: FSCR3: 1 LOCKED EFSEN SOURCE XXXX 1 0 XXXX 1 1 <>11XX 1 1 <>11XX 1 1 11XX Note 1: That is, when OPSTATE:T0STATE=100. Note Don’t Care Note 3: None of the SYNCn pins is used. The internal 2kHz alignment generators free-run at their existing alignment. See Section 7.9.5. ...
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... DS3104-SE signal is qualified, the FSYNC/MFSYNC 2kHz alignment generator is always synchronized by SYNCn, and, therefore, FSYNC and MFSYNC are always falling-edge aligned with SYNCn. When FSCR2:INDEP = 0, the T0 DPLL 2kHz alignment generator is also synchronized with the FSYNC/MFSYNC 2kHz alignment generator to falling-edge align all T0-derived output clocks with SYNCn. When INDEP = 1, the T0 DPLL 2-kHz alignment generator is not synchronized with the FSYNC/MFSYNC 2kHz alignment generator and continues to free-run with its existing 2kHz alignment ...
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... Burst Writes. See Figure followed by the first data byte to be written. The DS3104-SE receives the first data byte on SDI, writes it to the specified register, increments its internal address register, and prepares to receive the next data byte. If the master continues to transmit, the DS3104-SE continues to write the data received and increment its address counter. After the address counter reaches 3FFFh it rolls over to address 0000h and continues to increment ...
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... Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the DS3104-SE is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support this option, the bus master must not drive the SDI/SDO line when the DS3104-SE is transmitting. ...
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... DS3104-SE Figure 7-6. SPI Bus Transactions Single-Byte Write CS R/W Register Address Burst SDI 0 (Write) SDO Single-Byte Read CS R/W Register Address Burst SDI 1 (Read) SDO Burst Write CS R/W Register Address Burst Data Byte 1 SDI 0 (Write) SDO Burst Read CS R/W Register Address Burst SDI 1 (Read) Rev: 012108 ...
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... Initialization After power-up or reset, a series of writes must be done to the DS3104-SE to tune it for optimal performance. This series of writes is called the initialization script. Each DS3104-SE die revision has a different initialization script. Download the latest initialization scripts from the DS3104-SE webpage at www.maxim-ic.com/DS3104-SE, or email telecom ...
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... Register Descriptions The DS3104-SE has an overall address range from 000h to 1FFh. In each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “—“ are reserved and must be written with 0. Writing other values to these registers may put the device in a factory test mode resulting in undefined operation. Bits labeled “ ...
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... DS3104-SE 8.4 Register Definitions Table 8-1. Register Map Note: Register names are hyperlinks to register definitions. Underlined fields are read-only. ADDR REGISTER BIT 7 00h ID1 01h ID2 02h REV 03h TEST1 PALARM 05h MSR1 IC8 06h MSR2 STATE SRFAIL 07h FREQ3 — 08h ...
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... DS3104-SE ADDR REGISTER BIT 7 3Ah MCR8 OC5SF 3Bh MCR9 AUTOBW 3Ch MCLK1 3Dh MCLK2 40h HOCR3 AVG 41h DLIMIT1 42h DLIMIT2 — 43h IER1 IC8 44h IER2 STATE SRFAIL 45h IER3 FSMON T4LOCK 46h DIVN1 47h DIVN2 48h MCR10 — ...
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... DS3104-SE ADDR REGISTER BIT 7 72h PBOFF — 73h PHLIM1 FLEN 74h PHLIM2 CLEN MCPDEN USEMCPD 76h PHMON NW 77h PHASE1 78h PHASE2 79h PHLKTO PHLKTOM[1:0] 7Ah FSCR1 2K8KSRC 7Bh FSCR2 INDEP 7Ch FSCR3 RECAL 7Dh INTCR — 7Eh PROT Register Map Color Coding ...
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... DS3104-SE Register Name: ID1 Register Description: Device Identification Register, LSB Register Address: 00h Bit # 7 6 Name Default 0 0 Bits Device ID (ID[7:0]). ID[15:0] = 0C20h = 3104 decimal. Register Name: ID2 Register Description: Device Identification Register, MSB Register Address: 01h Bit # 7 6 Name Default ...
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... DS3104-SE Register Name: TEST1 Register Description: Test Register 1 (Not Normally Used) Register Address: 03h Bit # 7 6 Name PALARM D180 Default 0 0 Bit 7: Phase Alarm (PALARM). This real-time status bit indicates the state of the T0 DPLL phase-lock detector. See Section 7.7.6. (Note: This is not the same as T0STATE = Locked.) ...
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... DS3104-SE Register Name: MSR1 Register Description: Master Status Register 1 Register Address: 05h Bit # 7 6 Name IC8 — Default 1 0 Bits 7 and Input Clock Status Change (IC8 and IC[6:1]). Each of these latched status bits is set to 1 when the corresponding VALSR1 status bit changes state (set or cleared). Each bit is cleared when written with a 1 ...
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... DS3104-SE Register Name: MSR3 Register Description: Master Status Register 3 Register Address: 08h Bit # 7 6 Name FSMON T4LOCK Default 0 1 Bit 7: Frame-Sync Input Monitor Alarm (FSMON). This latched status bit is set to 1 when OPSTATE:FSMON transitions from FSMON is cleared when written with a 1. When FSMON is set it can cause an interrupt request on the INTREQ pin if the FSMON interrupt enable bit is set in the Bit 6: T4 DPLL Lock Status Change (T4LOCK) ...
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... DS3104-SE Register Name: OPSTATE Register Description: Operating State Register Register Address: 09h Bit # 7 6 Name FSMON T4LOCK Default 1 0 Bit 7: Frame-Sync Input Monitor Alarm (FSMON). This real-time status bit indicates the current status of the frame-sync input monitor. See Section 7.9. alarm 1 = Alarm Bit 6: T4 DPLL Lock Status (T4LOCK) ...
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... DS3104-SE Register Name: PTAB1 Register Description: Priority Table Register 1 Register Address: 0Ah Bit # 7 6 Name Default 0 0 Bits Highest Priority Valid Reference (REF1[3:0]). This real-time status field indicates the highest priority valid input reference. When T4T0 = 0 in the the T0 DPLL. When T4T0 = 1, it indicates the highest priority reference for the T4 DPLL. Note that an input ...
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... DS3104-SE Register Name: PTAB2 Register Description: Priority Table Register 2 Register Address: 0Bh Bit # 7 6 Name Default 0 0 Bits Third Highest Priority Valid Reference (REF3[3:0]). This real-time status field indicates the third highest priority validated input reference. When T4T0 = 0 in the highest priority reference for the T0 DPLL ...
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... DS3104-SE Register Name: FREQ1 Register Description: Frequency Register 1 Register Address: 0Ch Bit # 7 6 Name Default 0 0 Note: The FREQ1, FREQ2, and FREQ3 registers must be read consecutively. See Section 8.3. Bits Current DPLL Frequency (FREQ[7:0]). The full 19-bit FREQ[18:0] field spans this register, FREQ2 and FREQ3. FREQ is a two’ ...
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... DS3104-SE Register Name: VALSR1 Register Description: Input Clock Valid Status Register 1 Register Address: 0Eh Bit # 7 6 Name IC8 — Default 0 0 Bits 7 and Input Clock Valid Status (IC8 and IC[6:1]). Each of these real-time status bits is set to 1 when the corresponding input clock is valid. An input is valid if it has no active alarms (ACT = 0, LOCK = 0 in the ...
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... DS3104-SE Register Name: ISR1 Register Description: Input Status Register 1 Register Address: 10h Bit # 7 6 Name — — Default 0 0 Bit 5: Activity Alarm for Input Clock 2 (ACT2). This real-time status bit is set to 1 when the leaky bucket accumulator for IC2 reaches the alarm threshold specified in the BUCKET field of ICR1) ...
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... DS3104-SE Register Name: ISR3 Register Description: Input Status Register 3 Register Address: 12h Bit # 7 6 Name — — Default 0 0 This register has the same behavior as the ISR1and Register Name: ISR4 Register Description: Input Status Register 4 Register Address: 13h Bit # 7 6 Name — ...
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... DS3104-SE Register Name: MSR4 Register Description: Master Status Register 4 Register Address: 17h Bit # 7 6 Name — HORDY Default 0 0 Bit 6: Holdover Frequency Ready (HORDY). This latched status bit is set to 1 when the T0 DPLL has a holdover value that has been averaged over the 1-second holdover averaging period. HORDY is cleared when written with a 1 ...
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... DS3104-SE Register Name: IPR1 Register Description: Input Priority Register 1 Register Address: 18h Bit # 7 Name Default (T0) 0 Default (T4) 0 Bits Priority for Input Clock 2 (PRI2[3:0]). Priority 0001 is highest; priority 1111 is lowest. When MCR11:T4T0 = 0, PRI2 configures IC2’s priority for the T0 DPLL. When T4T0 = 1, PRI2 configures IC2’s priority for the T4 path ...
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... DS3104-SE Register Name: IPR3 Register Description: Input Priority Register 3 Register Address: 1Ah Bit # 7 Name Default (T0) 0 Default (T4) 0 These registers have the same behavior as Register Name: IPR4 Register Description: Input Priority Register 4 Register Address: 1Bh Bit # 7 Name Default (T0) 0 Default (T4) ...
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... DS3104-SE Register Name: ICR1, ICR2, ICR3, ICR4, ICR5, ICR6, ICR8, ICR9 Register Description: Input Configuration Register Register Address: 20h, 21h, 22h, 23h, 24h, 25h, 27h, 28h Bit # 7 6 Name DIVN LOCK8K Default 0 0 Note: These registers are identical in function. ICRx is the control register for input clock ICx. ...
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... DS3104-SE DIVN = 1 and LOCK8K = 1: (Alternate direct-lock frequency decode) 0000 = 10MHz (internally divided down to 5MHz) 0001 = 25MHz (internally divided down to 5MHz) 0010 = 62.5MHz (internally down to 31.25MHz) 0011 = 125MHz (internally down to 31.25MHz) 0100 = 156.25MHz (differential inputs only; internally divided down to 31.25MHz) 0101–1111 = undefined FREQ[3:0] Default Values: ICR1– ...
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... DS3104-SE Register Name: MCR1 Register Description: Master Configuration Register 1 Register Address: 32h Bit # 7 6 Name RST — Default 0 0 Bit 7: Device Reset (RST). When this bit is high the entire device is held in reset, and all register fields, except the RST bit itself, are reset to their default states. When RST is active, the register fields with pin-programmed defaults do not latch their values from the corresponding input pins ...
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... DS3104-SE Register Name: MCR2 Register Description: Master Configuration Register 2 Register Address: 33h Bit # 7 6 Name — — Default 0 0 Bits DPLL Force Selected Reference (T0FORCE[3:0]). This field provides a way to force a specified input clock to be the selected reference for the T0 DPLL. Internally this is accomplished by forcing the clock to have the highest priority (as specified in PTAB1:REF1) ...
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... DS3104-SE Register Name: MCR3 Register Description: Master Configuration Register 3 Register Address: 34h Bit # 7 6 Name AEFSEN LKATO Default 1 1 Bit 7: Auto External Frame Sync Enable (AEFSEN). This bit has two functions depending on the external frame sync mode. See section 7.9.1. SYNC1 Modes SYNC1 Manual Mode: External frame sync is manually enabled on the SYNC1 pin when EFSEN = 1 ...
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... DS3104-SE Register Name: MCR4 Register Description: Master Configuration Register 4 Register Address: 35h Bit # 7 6 Name LKT4T0 — Default 0 0 Bit 7: Lock (LKT4T0). When this bit is set to 1 (and T0CR1:T4APT0 = 0) all output clocks are generated from the T0 DPLL, and the T4CR1:T4FREQ field selects the frequency of the T4 APLL. See Section 7.8.2.2. When LKT4T0 = 0, the T4 APLL can be locked to either the T4 DPLL or the T0 DPLL, depending on the setting of T0CR1:T4APT0 ...
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... DS3104-SE Register Name: MCR5 Register Description: Master Configuration Register 5 Register Address: 36h Bit # 7 6 Name RSV4 RSV3 Default 0 0 Bits Reserved Bit (RSV[4:1]). These bits are reserved for future use, and can be written to and read back. Bit 3: Input Clock 2 Signal Format (IC2SF). For backward compatibility this bit can be written to and read back, but it does not affect the IC2POS/NEG inputs pins ...
Page 77
... DS3104-SE Register Name: OCR6 Register Description: Output Configuration Register 6 Register Address: 37h Bit # 7 6 Name — OC5EN Default 0 1 Bit 6: OC5 Output Enable (OC5EN). Enables the OC5 output pin Output clock pin disabled, drives low Output clock pin controlled by OCR3.OFREQ5. ...
Page 78
... DS3104-SE Register Name: MCR6 Register Description: Master Configuration Register 6 Register Address: 38h Bit # 7 6 Name DIG2AF DIG2SS Default 0 see below Bit 7: Digital Alternate Frequency (DIG2AF). Selects alternative frequencies Digital2 DS1 frequency specified by DIG2SS and MCR7:DIG2F Digital2 6.312MHz, 10MHz 19.44MHz frequency specified by DIG2SS and MCR7:DIG2F. ...
Page 79
... DS3104-SE Register Name: MCR7 Register Description: Master Configuration Register 7 Register Address: 39h Bit # 7 6 Name DIG2F[1:0] Default 0 0 Bits Digital2 Frequency (DIG2F[1:0]). This field, MCR6:DIG2SS, and MCR6:DIG2AF configure the frequency of the Digital2 clock synthesizer. DIG2AF = 0 DIG2SS = 1 DIG2SS = 1544kHz ...
Page 80
... DS3104-SE Register Name: MCR8 Register Description: Master Configuration Register 8 Register Address: 3Ah Bit # 7 6 Name OC5SF[1:0] Default 0 0 For Rev A2 devices, in LVPECL mode the differential output voltage will be higher than the MAX V Table 10-6 unless an adjustment register is written with the proper value. If differential voltages larger than ...
Page 81
... DS3104-SE Register Name: MCR9 Register Description: Master Configuration Register 9 Register Address: 3Bh Bit # 7 6 Name AUTOBW — Default 1 1 Bit 7: Automatic Bandwidth Selection (AUTOBW). See Section 7.7. Always selects locked bandwidth from the 1 = Automatically selects either locked bandwidth register) as appropriate. Bit 3: Limit Integral Path (LIMINT). When this bit is set to 1, the T0 DPLL’s integral path is limited (i.e., frozen) ...
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... DS3104-SE Register Name: MCLK1 Register Description: Master Clock Frequency Adjustment Register 1 Register Address: 3Ch Bit # 7 6 Name Default 1 0 Note: The MCLK1 and MCLK2 registers must be read consecutively and written consecutively. See Section 8.3. Bits Master Clock Frequency Adjustment (MCLKFREQ[7:0]). The full 16-bit MCLKFREQ[15:0] field spans this register and MCLK2 ...
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... DS3104-SE Register Name: DLIMIT1 Register Description: DPLL Frequency Limit Register 1 Register Address: 41h Bit # 7 6 Name Default 0 1 Note: The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See Section 8.3. Bits DPLL Hard Frequency Limit (HARDLIM[7:0]). The full 10-bit HARDLIM[9:0] field spans this register and DLIMIT2 ...
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... DS3104-SE Register Name: IER1 Register Description: Interrupt Enable Register 1 Register Address: 43h Bit # 7 6 Name IC8 — Default 0 0 Bits 7 and Interrupt Enable for Input Clock Status Change (IC8 and IC[6:1]). Each of these bits is an interrupt enable control for the corresponding bit in the ...
Page 85
... DS3104-SE Register Name: IER3 Register Description: Interrupt Enable Register 3 Register Address: 45h Bit # 7 6 Name FSMON T4LOCK Default 0 0 Bit 7: Interrupt Enable for Frame-Sync Input Monitor Alarm (FSMON). This bit is an interrupt enable for the FSMON bit in the MSR3 register. ...
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... DS3104-SE Register Name: DIVN1 Register Description: DIVN Register 1 Register Address: 46h Bit # 7 6 Name Default 1 1 Note: The DIVN1 and DIVN2 registers must be read consecutively and written consecutively. See Section 8.3. Bits DIVN Factor (DIVN[7:0]). The full 16-bit DIVN[15:0] field spans this register and DIVN2. This field contains the integer value used to divide the frequency of input clocks that are configured for DIVN mode ...
Page 87
... DS3104-SE Register Name: MCR10 Register Description: Master Configuration Register 10 Register Address: 48h Bit # 7 6 Name — SRFPIN Default 1 0 Bit 6: SRFAIL Pin Enable (SRFPIN). When this bit is set to 1, the SRFAIL pin is enabled. When enabled the SRFAIL pin follows the state of the SRFAIL status bit in the indication of the failure of the current reference ...
Page 88
... DS3104-SE Register Name: DLIMIT3 Register Description: DPLL Frequency Limit Register 3 Register Address: 4Dh Bit # 7 6 Name FLLOL Default 1 0 Bit 7: Frequency Limit Loss-of-Lock (FLLOL). When this bit is set to 1, the T0 DPLL and the T4 DPLL internally declare loss-of-lock when their hard limits are reached. The T0 DPLL hard frequency limit is set in the ...
Page 89
... DS3104-SE Register Name: OCR5 Register Description: Output Configuration Register 1 Register Address: 4Fh Bit # 7 6 Name — AOF7 Default 0 0 Bit 6: Alternate Output Frequency Mode Select 7 (AOF7). This bit controls the decoding of the OCR4.OFREQ7 field for the OC7 pin Standard decodes 1 = Alternate decodes Bit 5: Alternate Output Frequency Mode Select 6 (AOF6) ...
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... DS3104-SE Register Name: LB0U Register Description: Leaky Bucket 0 Upper Threshold Register Register Address: 50h Bit # 7 6 Name Default 0 0 Bits Leaky Bucket 0 Upper Threshold (LB0U[7:0]). When the leaky bucket accumulator is equal to the value stored in this field, the activity monitor declares an activity alarm by setting the input clock’s ACT bit in the ...
Page 91
... DS3104-SE Register Name: LB1U, LB2U, LB3U Register Description: Leaky Bucket 1/2/3 Upper Threshold Register Register Address: 54h, 58h, 5Ch Bit # 7 6 Name Default 0 0 Bits Leaky Bucket “x” Upper Threshold (LBxU[7:0]). See the Registers LB1U, LB1L, LB1S, and Registers LB2U, LB2L, LB2S, and ...
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... DS3104-SE Register Name: OCR1 Register Description: Output Configuration Register 1 Register Address: 60h Bit # 7 6 Name OFREQ2[3:0] Default 0 0 Bits Output Frequency of OC2 (OFREQ2[3:0]). This field specifies the frequency of output clock OC2. The frequencies of the T0 APLL and the T4 APLL are configured in the and Digital2 frequencies are configured in the controlled by the value of the OCR5 ...
Page 93
... DS3104-SE 1010 = T0 APLL frequency divided by 4 1011 = T4 APLL frequency divided by 64 1100 = T4 APLL frequency divided by 48 1101 = T4 APLL frequency divided by 16 1110 = T4 APLL frequency divided by 8 1111 = T4 APLL frequency divided by 4 AOF1 = 1: (alternate decodes) 0000 = Output disabled (i.e., low) 0001 = T0 APLL frequency divided by 64 ...
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... DS3104-SE Register Name: OCR2 Register Description: Output Configuration Register 2 Register Address: 61h Bit # 7 6 Name OFREQ4[3:0] Default 0 0 Bits Output Frequency of OC4 (OFREQ4[3:0]). This field specifies the frequency of output clock OC4. The frequencies of the T0 APLL and T4 APLL are configured in the Digital2 frequencies are configured in the by the value of the OCR5 ...
Page 95
... DS3104-SE 1010 = T0 APLL frequency divided by 4 1011 = T4 APLL frequency divided by 64 1100 = T4 APLL frequency divided by 48 1101 = T4 APLL frequency divided by 16 1110 = T4 APLL frequency divided by 8 1111 = T4 APLL frequency divided by 4 AOF3 = 1: (alternate decodes) 0000 = Output disabled (i.e., low) 0001 = T0 APLL frequency divided by 64 ...
Page 96
... DS3104-SE Register Name: OCR3 Register Description: Output Configuration Register 3 Register Address: 62h Bit # 7 6 Name OFREQ6[3:0] Default 0 0 Bits Output Frequency of OC6 (OFREQ6[3:0]). This field specifies the frequency of output clock output OC6. The frequencies of the T0 APLL and T4 APLL are configured in the Digital1 and Digital2 frequencies are configured in the is controlled by the value of the OCR5 ...
Page 97
... DS3104-SE 1010 = T0 APLL frequency divided by 4 1011 = T4 APLL frequency divided by 2 1100 = T4 APLL frequency divided by 48 1101 = T4 APLL frequency divided by 16 1110 = T4 APLL frequency divided by 8 1111 = T4 APLL frequency divided by 4 AOF5 = 1: (alternate decodes) 0000 = Output disabled (i.e., low) 0001 = T0 APLL frequency divided by 2 ...
Page 98
... DS3104-SE Register Name: OCR4 Register Description: Output Configuration Register 4 Register Address: 63h Bit # 7 6 Name MFSEN FSEN Default 1 1 Bit 7: MFSYNC Enable (MFSEN). This configuration bit enables the 2kHz output on the MFSYNC pin. See Section 7.8.2. Disabled, driven low 1 = Enabled, output is 2kHz Bit 6: FSYNC Enable (FSEN) ...
Page 99
... DS3104-SE Register Name: T4CR1 Register Description: T4 DPLL Configuration Register 1 Register Address: 64h Bit # 7 6 Name — — Default 0 0 Bits APLL Frequency (T4FREQ[3:0]). When T0CR1:T4APT0 = 0, the T4 APLL DFS is connected to the T4 DPLL, and this field configures the T4 APLL DFS frequency. The T4 APLL DFS frequency affects the ...
Page 100
... DS3104-SE Register Name: T0CR1 Register Description: T0 DPLL Configuration Register 1 Register Address: 65h Bit # 7 6 Name T4MT0 T4APT0 Default 0 1 Bit 7: T4 Measure T0 Phase (T4MT0). When this bit is set to 1 the T4 DPLL goes to the free-run mode, and the T4 phase detector is configured to measure the phase difference between the selected T0 DPLL input clock and the selected the T4 DPLL input clock ...
Page 101
... DS3104-SE Register Name: T4BW Register Description: T4 Bandwidth Register Register Address: 66h Bit # 7 6 Name 0 0 Default 0 0 Bits DPLL Bandwidth (T4BW[2:0]). See Section 7.7. 18Hz 01 = 35Hz 10 = 70Hz 11 = {unused value, undefined} Register Name: T0LBW Register Description: T0 DPLL Locked Bandwidth Register ...
Page 102
... DS3104-SE Register Name: T0ABW Register Description: T0 DPLL Acquisition Bandwidth Register Register Address: 69h Bit # 7 6 Name — — Default 0 0 Bit 4: Reserved Bit 1 (RSV1). This bit is reserved for future use, it can be written to and read back. Bits DPLL Acquisition Bandwidth (T0ABW[3:0]). This field configures the bandwidth of the T0 DPLL when acquiring lock ...
Page 103
... DS3104-SE Register Name: T4CR2 Register Description: T4 Configuration Register 2 Register Address: 6Ah Bit # 7 6 Name — Default 0 0 Bits Phase Detector 2 Gain 8kHz (PD2GA8K[2:0]). This field specifies the gain of the T4 phase detector 2 with an input clock of 8kHz or less. This value is only used if automatic gain selection is enabled by setting PD2EN ...
Page 104
... DS3104-SE Register Name: T0CR2 Register Description: T0 Configuration Register 2 Register Address: 6Bh Bit # 7 6 Name — Default 0 0 Bits Phase Detector 2 Gain, 8kHz (PD2G8K[2:0]). This field specifies the gain of the T0 phase detector 2 with an input clock of 8kHz or less. This value is only used if automatic gain selection is enabled by setting PD2EN ...
Page 105
... DS3104-SE Register Name: T4CR3 Register Description: T4 Configuration Register 3 Register Address: 6Ch Bit # 7 6 Name PD2EN Default 1 1 Bit 7: Phase Detector 2 Gain Enable (PD2EN). When this bit is set to 1, the T4 phase detector 2 is enabled and the gain is determined by the input locking frequency. If the frequency is greater than 8kHz, the gain is set by the PD2G field ...
Page 106
... DS3104-SE Register Name: GPCR Register Description: GPIO Configuration Register Register Address: 6Eh Bit # 7 6 Name GPIO4D GPIO3D Default 0 0 Bit 7: GPIO4 Direction (GPIO4D). This bit configures the data direction for the GPIO4 pin. When GPIO4 is an input its current state can be read from GPSR:GPIO4. When GPIO4 is an output, its value is controlled by the GPIO4O configuration bit ...
Page 107
... DS3104-SE Register Name: GPSR Register Description: GPIO Status Register Register Address: 6Fh Bit # 7 6 Name — — Default 0 0 Bit 3: GPIO4 State (GPIO4). This bit indicates the current state of the GPIO4 pin Low 1 = High Bit 2: GPIO3 State (GPIO3). This bit indicates the current state of the GPIO3 pin. ...
Page 108
... DS3104-SE Register Name: OFFSET1 Register Description: Phase Offset Register 1 Register Address: 70h Bit # 7 6 Name Default 0 0 Note: The OFFSET1 and OFFSET2 registers must be read consecutively and written consecutively. See Section 8.3. Bits Phase Offset (OFFSET[7:0]). The full 16-bit OFFSET[15:0] field spans this register and the register. OFFSET is a two’ ...
Page 109
... DS3104-SE Register Name: PBOFF Register Description: Phase Build-Out Offset Register Register Address: 72h Bit # 7 6 Name — — Default 0 0 Bits Phase Build-Out Offset Register (PBOFF[5:0]). An uncertainty 5ns is introduced each time a phase build-out event occurs. This uncertainty results in a phase hit on the output. Over a large number of phase build-out events the mean error should be zero. The PBOFF field specifies a fixed offset for each phase build-out event to skew the average error toward zero. This field is a two’ ...
Page 110
... DS3104-SE Register Name: PHLIM2 Register Description: Phase Limit Register 2 Register Address: 74h Bit # 7 6 Name CLEN MCPDEN Default 1 0 Bit 7: Coarse Phase Limit Enable (CLEN). This configuration bit enables the coarse phase limit specified in the COARSELIM[3:0] field. This field controls both T0 and T4. See Section 7.7.6. ...
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... DS3104-SE Register Name: PHMON Register Description: Phase Monitor Register Register Address: 76h Bit # 7 6 Name NW — Default 0 0 Bit 7: Low-Frequency Input Clock Noise Window (NW). For 2kHz, 4kHz, or 8kHz input clocks, this configuration bit enables a ±5% tolerance noise window centered around the expected clock edge location. Noise-induced edges outside this window are ignored, reducing the possibility of phase hits on the output clocks. This only applies to the T0 DPLL and should be enabled only when the T0 DPLL is locked to an input and the 180° ...
Page 112
... DS3104-SE Register Name: PHASE1 Register Description: Phase Register 1 Register Address: 77h Bit # 7 6 Name Default 0 0 Note: The PHASE1 and PHASE2 registers must be read consecutively. See Section 8.3. Bits Current DPLL Phase (PHASE[7:0]). The full 16-bit PHASE[15:0] field spans this register and the PHASE2 register. PHASE is a two’ ...
Page 113
... DS3104-SE Register Name: FSCR1 Register Description: Frame-Sync Configuration Register 1 Register Address: 7Ah Bit # 7 6 Name 2K8KSRC Default 0 0 Bit 7: 2kHz/8kHz Source (2K8KSRC). This configuration bit specifies the source for the 2kHz and 8kHz outputs available on clock outputs. When MCR4:LKT4T0 = always connected to the T0 DPLL. See Section 7.8.2.3. ...
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... DS3104-SE Register Name: FSCR2 Register Description: Frame-Sync Configuration Register 2 Register Address: 7Bh Bit # 7 6 Name INDEP OCN Default 0 0 Bit 7: Independent Frame Sync and Multiframe Sync (INDEP). When this bit is set to 0, the 8kHz frame sync on FSYNC and the 2kHz multiframe sync on MFSYNC are aligned with the other output clocks when synchronized with the SYNCn input ...
Page 115
... DS3104-SE Register Name: FSCR3 Register Description: Frame-Sync Configuration Register 3 Register Address: 7Ch Bit # 7 6 Name RECAL Default 0 0 Bit 7: Phase Offset Recalibration (RECAL). When set to 1, this configuration bit causes a recalibration of the phase offset between the output clocks and the selected reference. This process puts the DPLL into mini holdover, ...
Page 116
... DS3104-SE Register Name: INTCR Register Description: Interrupt Configuration Register Register Address: 7Dh Bit # 7 6 Name — — Default 0 0 Bit 3: INTREQ Pin Mode (LOS). When GPO = 0, this bit selects the function of the INTREQ pin The INTREQ/LOS pin indicates interrupt requests 1 = The INTREQ/LOS pin indicates the real-time state of the selected reference activity monitor (see Section 7 ...
Page 117
... JTAG Test Access Port and Boundary Scan 9.1 JTAG Description The DS3104-SE supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and ...
Page 118
... DS3104-SE 9.2 JTAG TAP Controller State Machine Description This section discusses the operation of the TAP controller state machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. Each of the states denoted in Figure 9-2 is described in the following paragraphs. ...
Page 119
... DS3104-SE Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process. Pause-IR. Shifting of the instruction register is halted temporarily. With JTMS high, a rising edge on JTCLK puts the controller in the Exit2-IR state ...
Page 120
... JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the Update- IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction parallel output. Table 9-1 shows the instructions supported by the DS3104-SE and their respective operational binary codes. Table 9-1. JTAG Instruction Codes INSTRUCTIONS ...
Page 121
... Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. The device identification code for the DS3104-SE is shown in Table 9-2. Table 9-2. JTAG ID Code DEVICE ...
Page 122
... DS3104-SE 10. Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin with Respect to V Supply Voltage Range (V ) with Respect Supply Voltage Range (V ) with Respect to V DDIO Ambient Operating Temperature Range…………………………………………………………..-40°C to +85°C (Note 1) Junction Operating Temperature Range… ...
Page 123
... DS3104-SE Table 10-3. CMOS/TTL Pins = 1.8V ±10 3.3V ±5 DDIO PARAMETER Input High Voltage Input Low Voltage Input Leakage Input Leakage, Pins with Internal Pullup Resistor (50kΩ typ) Input Leakage, Pins with Internal Pulldown Resistor (50kΩ typ) Output Leakage (when High-Z) Output High Voltage ( ...
Page 124
... DS3104-SE Table 10-6. LVPECL Level-Compatible Output Pins = 1.8V ±10 3.3V ±5 DDIO PARAMETER Differential Output Voltage Output Offset (Common Mode) Voltage Difference in Magnitude of Output Differential Voltage for Complementary States Note 1: With 100 Ω load across the differential outputs. Note 2: The differential outputs can easily be interfaced to LVDS, LVPECL, and CML inputs on neighboring ICs using a few external passive components ...
Page 125
... DS3104-SE Figure 10-3. Recommended Termination for LVPECL-Compatible Output Pins DS3104 LVPECL LEVEL- COMPATIBLE OUTPUTS Rev: 012108 3.3V 82Ω 82Ω 50Ω OCnPOS 0.01μF 50Ω OCnNEG 130Ω 130Ω GND LVPECL RECEIVER 125 of 136 ...
Page 126
... DS3104-SE 10.2 Input Clock Timing Table 10-7. Input Clock Timing = 1.8V ±10 3.3V ±5 DDIO PARAMETER CMOS/TTL Input Pins Input Clock Period LVDS/LVPECL Input Pins Input Clock High, Low Time 10.3 Output Clock Timing Table 10-8. Input Clock to Output Clock Delay INPUT OUTPUT FREQUENCY FREQUENCY ...
Page 127
... DS3104-SE 10.4 SPI Interface Timing Table 10-10. SPI Interface Timing = 1.8V ±10 3.3V ±5 DDIO PARAMETER (Note 1) SCLK Frequency SCLK Cycle Time CS Setup to First SCLK Edge CS Hold Time After Last SCLK Edge SCLK High Time SCLK Low Time SDI Data Setup Time SDI Data Hold Time ...
Page 128
... DS3104-SE Figure 10-4. SPI Interface Timing Diagram CPHA = SUC CYC SCLK, CPOL=0 t CLKH t SCLK, CLKL CPOL SUI HDI SDI SDO CPHA = SUC CYC SCLK, CPOL=0 t CLKH t SCLK, CLKL CPOL=1 t SUI SDI SDO Rev: 012108 t CLKL t CLKH ...
Page 129
... DS3104-SE 10.5 JTAG Interface Timing Table 10-11. JTAG Interface Timing = 1.8V ±10 3.3V ±5 DDIO PARAMETER JTCLK Clock Period JTCLK Clock High/Low Time (Note 1) JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay JTCLK to JTDO High-Z Delay (Note 2) JTRST Width Low Time Note 1: Clock can be stopped high or low ...
Page 130
... DS3104-SE 10.6 Reset Pin Timing Table 10-12. Reset Pin Timing = 1.8V ±10 3.3V ±5 DDIO PARAMETER RST Low Time (Note 1) SONSDH, SRCSW Setup Time to RST SONSDH, SRCSW Hold Time from RST RST should be held low while the REFCLK oscillator stabilizes recommended to force RST low during power-up. The ...
Page 131
... DS3104-SE 11. Pin Assignments Table 11-1 lists pin assignments sorted in alphabetical order by pin name. arranged by pin number. Table 11-1. Pin Assignments Sorted by Signal Name PIN NAME PIN NUMBER AVDD_PLL1 AVDD_PLL2 C2 AVDD_PLL3 AVDD_PLL4 AVSS_PLL1 AVSS_PLL2 C3 AVSS_PLL3 AVSS_PLL4 G2 CPHA CPOL FSYNC H1 IC1NEG IC1POS H5 IC2NEG ...
Page 132
... DS3104-SE Figure 11-1. Pin Assignment Diagram AVSS_PLL1 TEST INTREQ/ B AVDD_PLL1 LOS C REFCLK AVDD_PLL2 AVSS_PLL2 D OC4NEG OC4POS E OC5NEG OC5POS F AVSS_PLL3 AVDD_PLL3 AVDD_PLL4 G SRCSW AVSS_PLL4 H FSYNC OC6POS J MFSYNC OC6NEG High-Speed Analog Low-Speed Analog High-Speed Digital Low-Speed Digital V 3.3V DDIO V 3.3V or 2.5V DDIOB V 1.8V DD Analog V 1 ...
Page 133
... DS3104-SE 12. Package Information The latest package outline drawing for the 10mm x 10mm, 81-lead CSBGA package is found on the Maxim website at www.maxim-ic.com/DallasPackInfo. Table 12-1. CSBGA Package Thermal Properties, Natural Convection PARAMETER Ambient Temperature (Note 1) Junction Temperature Theta-JA (θ ) (Note 2) JA Theta-JB (θ ...
Page 134
... DS3104-SE 13. Acronyms and Abbreviations AIS Alarm Indication Signal AMI Alternate Mark Inversion APLL Analog Phase-Locked Loop BITS Building Integrated Timing Supply BPV Bipolar Violation DFS Digital Frequency Synthesis DPLL Digital Phase-Locked Loop ESF Extended Superframe EXZ Excessive Zeros GbE Gigabit Ethernet ...
Page 135
... DS3104-SE 14. Data Sheet Revision History REVISION DATE 060507 Initial data sheet release. Corrected typo in Features bullet, Programmable PLL Bandwidth, from 1Hz to 0.1Hz (0.1Hz to 070507 400Hz). Added reference to G.8262 to In the OC3B pin description in In Table 6-3, changed pin name INTREQ/SRFAIL to INTREQ/LOS and changed the pin description to clarify its non-INTREQ function ...
Page 136
... DS3104-SE Data Sheet Revision History (continued) REVISION DATE Updated Section 7.9 the device. Also updated MCR3:AEFSEN, MCR3:EFSEN, FSCR3:SOURCE and 012108 FSCR1:SYNCSRC to match. In Section 10, added Note 1 to the Absolute Maximum Ratings. Rev: 012108 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied ...