ds3104 Maxim Integrated Products, Inc., ds3104 Datasheet - Page 135

• Manufacturer Part Number: ds3104
• Description: Ds3104 Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

14.
Rev: 012108
________________________________________________________________________________________ DS3104-SE
REVISION
060507
070507
071807
110207
DATE
Data Sheet Revision History
Initial data sheet release.
Corrected typo in Features bullet, Programmable PLL Bandwidth, from 1Hz to 0.1Hz (0.1Hz to
400Hz).
Added reference to G.8262 to
In the OC3B pin description in
In
description to clarify its non-INTREQ function.
In
supply for T0 APLL2 rather than T0 APLL.
In Section 7.11, emphasized the need for RST pin assertion and added requirement to least
100µs after reset is deasserted before initializing the device.
In the MSR2:SRFAIL bit description, deleted references to the INTREQ/SRFAIL pin and to
INTCR:SRFAIL.
In the
“—“.
Deleted reference to nonexistent PMPBEN bit in the
Changed INTCR:SRFAIL to LOS and changed its bit description to clarify function. Updated
references to this bit in other INTCR bit descriptions.
In
In
Added that custom output frequencies are also available for any multiple of 10kHz up to
388.79MHz.
Updated most of the typical jitter numbers in
Edited the text of Section
Added text and procedure related to LVPECL mode to the
MCR8, added text to clarify that the 00 decode for each field powers down the output.
Added “1000 = T0 selected reference” option to the OFREQ1 to OFREQ7 fields in the
registers.
In
192mA, changed I
52mA to reflect the power consumption of rev A2. Also added a clarification to Note 3 to define
what “enabled” means.
In
+100μA to reflect the slightly higher leakage current of rev A2.
Table
Table
Table
Figure
Table
Table 10-3
MCR4
6-3, changed pin name INTREQ/SRFAIL to INTREQ/LOS and changed the pin
6-6, corrected AVDD_PLL4 and AVSS_PLL4 descriptions to say they are the power
11-1, changed INTREQ to INTREQ/LOS.
10-2, changed I
11-1, changed INTREQ to INTREQ/LOS.
register description header, corrected typo by renaming bit 6 from “T4DIGFB” to
, changed I
DDIO
typical from 29mA to 41mA, and changed I
DD
ILPU
7.12
typical from 160mA to 153mA, changed I
min from -85μA to -100μA and changed I
Table
Table
for clarity.
1-1.
6-2, corrected typo by changing OC2BEN to OC3BEN.
DESCRIPTION
Table 7-14
OFFSET1
from Rev A2 characterization data.
MCR8
register.
register description; in
DDIO
DD
max from 45mA to
ILPD
max from 185mA to
max from +85μA to
OCR
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