ds3104 Maxim Integrated Products, Inc., ds3104 Datasheet - Page 37

• Manufacturer Part Number: ds3104
• Description: Ds3104 Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

7.8
A total of 16 output clock pins, OC1 to OC5, OC1B to OC5B, OC4POS/NEG to OC7POS/NEG, FSYNC, and
MFSYNC are available on the device. Output clocks OC1 to OC7 are individually configurable for a variety of
frequencies derived from either the T0 DPLL or the T4 DPLL. OC1B to OC5B are powered from a dedicated I/O
power pin that can be set to any voltage from 2.2V to 3.3V. Output clocks FSYNC and MFSYNC serve as 8kHz
frame-sync and 2kHz multiframe-sync outputs, respectively.
the output clock pins.
Table 7-6. Output Clock Capabilities
7.8.1 Signal Format Configuration
Output clocks OC4, OC5, OC6, and OC7 are LVDS-compatible, LVPECL level-compatible outputs. The type of
output can be selected or the output can be disabled using the OCnSF configuration bits in the
LVPECL level-compatible mode generates a differential signal that is large enough for most LVPECL receivers.
Some LVPECL receivers have a limited common mode signal range which can be accommodated for by using an
AC-coupled signal. The LVDS electrical specifications are listed in
termination is shown in
and the recommended LVPECL receiver termination is shown in
easily interfaced to LVDS, LVPECL, and CML inputs on neighboring ICs using a few external passive components.
See
The other output clocks are CMOS/TTL signal format.
7.8.2 Frequency Configuration
The frequency of output clocks OC1 to OC7 is a function of the settings used to configure the components of the
T0 and T4 PLL paths. These components are shown in the detailed block diagram of
The DS3104-SE uses digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master
clock (204.8MHz) is divided down to the desired output frequency by adding a number to an accumulator. The DFS
output is a coding of the clock output phase that is used by a special circuit to determine where to put the edges of
the output clock between the clock edges of the master clock. The edges of the output clock, however, are not
ideally located in time resulting in jitter with an amplitude typically less than 1ns pk-pk.
Rev: 012108
________________________________________________________________________________________ DS3104-SE
MFSYNC
OUTPUT
CLOCK
Maxim App Note HFAN-1.0
FSYNC
OC1B
OC2B
OC3B
OC4B
OC5B
OC1
OC2
OC3
OC4
OC5
OC4
OC5
OC6
OC7
Output Clock Configuration
LVDS/LVPECL
3.3V powered
2.5V or 3.3V
CMOS/TTL
CMOS/TTL
CMOS/TTL
FORMAT
SIGNAL
powered
Figure
10-1. The LVPECL level-compatible electrical specifications are listed in
for details.
Frequency selection per Section
8kHz frame sync with programmable pulse width and polarity.
2kHz multiframe sync with programmable pulse width and polarity.
FREQUENCIES SUPPORTED
Table 7-6
Figure
7.8.2.3
Table
provides more detail on the capabilities of
10-3. These differential outputs can be
10-5, and the recommended LVDS
and
Table 7-7
Figure
7-1.
to
Table
MCR8
7-13.
register. The
Table
37 of 136
10-6,