SSTUG32865 NXP Semiconductors, SSTUG32865 Datasheet
SSTUG32865
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SSTUG32865 Summary of contents
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... RDIMM applications Rev. 01 — 16 August 2007 1. General description The SSTUG32865 is a 1.8 V 28-bit register specifically designed for use on two rank by four (2R is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs ...
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... SSTUG32865ET/S Pb-free (SnAgCu solder ball compound) 4.1 Ordering options Table 2. Type number SSTUG32865ET/G SSTUG32865ET/S SSTUG32865_1 Product data sheet 13 mm, 0.65 mm ball pitch TFBGA package Package Name Description TFBGA160 plastic thin fine-pitch ball grid array package; 160 balls; body 9 TFBGA160 plastic thin fine-pitch ball grid array package; ...
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... Functional diagram VREF PARIN D0 D21 DCS0 CSGATEEN DCS1 DCS2 DCS3 DCKE0, 2 DCKE1 DODT0, 2 DODT1 RESET CK CK Fig 1. Functional diagram of SSTUG32865 SSTUG32865_1 Product data sheet 1.8 V DDR2-1G registered buffer with parity (CS ACTIVE) PARITY GENERATOR D Q AND 22 R CHECKER ...
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... Product data sheet 1.8 V DDR2-1G registered buffer with parity SSTUG32865ET/G SSTUG32865ET/S ball A1 index area Transparent top view Rev. 01 — 16 August 2007 SSTUG32865 002aad100 © NXP B.V. 2007. All rights reserved ...
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... VDDL GND VDDL VDDL VDDR GND VDDL VDDL GND PTYERR MCH Q3B Q12B n.c. MCH Q3A Q12A Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity Q21A Q19A Q18A Q17B Q21B Q19B Q18B QODT0B QODT1B GND GND Q20B GND ...
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... PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR2 register with parity (in JEDEC definition). Rev. 01 — 16 August 2007 SSTUG32865 © NXP B.V. 2007. All rights reserved ...
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... Input reference voltage for the SSTL_18 inputs. Two pins nominal (internally tied together) are used for increased reliability. Power supply voltage. Power supply voltage. Ground. Ball present but not connected to die. DD Rev. 01 — 16 August 2007 SSTUG32865 . © NXP B.V. 2007. All rights reserved ...
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... floating floating Inputs [ floating X or floating Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity Dn, DODTn, DCKEn Qn QCS0 ...
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... LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUG32865 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. A programming pin, SELDR, allows the user to select between two drive strength options by tying this pin either LOW or HIGH on the DIMM ...
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... Non-gating 7.3.2 Parity error checking and reporting The SSTUG32865 incorporates a parity function, whereby the signal received on input pin PARIN is received as parity to the register, one clock cycle later than the CS-gated inputs. The received parity bit is then compared to the parity calculated across these same inputs by the register parity logic to verify that the information has not been corrupted. The 22 CS-gated input signals will be latched and re-driven on the fi ...
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... NXP Semiconductors 7.3.4 Power-up sequence The reset function for the SSTUG32865 is similar to that of the SSTU32864 except that the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive clock cycles. RESET DCSn ACT ( PARIN PTYERR HIGH, LOW, or Don't care ...
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... PDMSS Output signal is dependent on the prior unknown event Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity PHL PLH CK to PTYERR HIGH or LOW © NXP B.V. 2007. All rights reserved. 4 002aaa984 ...
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... Fig 6. RESET switches from HIGH to LOW SSTUG32865_1 Product data sheet t INACT t PHL RESET PLH RESET to PTYERR HIGH, LOW, or Don't care . INACT(max) Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity HIGH or LOW © NXP B.V. 2007. All rights reserved. 002aaa985 ...
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... HIGH”. Fig 7. Parity logic diagram SSTUG32865_1 Product data sheet 1.8 V DDR2-1G registered buffer with parity Section 7 “Functional description” Rev. 01 — 16 August 2007 SSTUG32865 LATCHING AND (1) RESET FUNCTION 002aaa417 and Figure 4 “RESET © NXP B.V. 2007. All rights reserved. QnA QnB ...
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... Human Body Model (HBM); 1 100 pF Machine Model (MM 200 pF Conditions [1] [1] data inputs (Dn) [1] [1] data inputs (Dn) [2] RESET [2] RESET CK, CK CK, CK SELDR either HIGH or LOW SELDR either HIGH or LOW operating in free air SSTUB32865ET/G SSTUB32865ET/S Rev. 01 — 16 August 2007 SSTUG32865 Min Max 0.5 +2.5 [1] 0.5 +2.5 [ 100 ...
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... I ref and CK 0.9 V; ICR V = 600 mV 1 RESET GND 1 normal drive; instantaneous normal drive; steady-state high drive; instantaneous high drive; steady-state Rev. 01 — 16 August 2007 SSTUG32865 Min Typ Max Unit 1 0 ...
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... PARIN after CK and CK after RESET is taken HIGH. ACT(max) INACT(max) Conditions CK and CK to output CK and CK to PTYERR CK and CK to PTYERR from RESET to PTYERR [1][2] CK and CK to output RESET to output Conditions Rev. 01 — 16 August 2007 SSTUG32865 Min Typ Max Unit - - 550 MHz ...
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... V IH ref 250 mV (AC voltage levels) for differential inputs ref Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity = 50 ; input slew rate = 1 V/ns 0 DUT delay = 350 OUT (1) ...
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... PLH PHL 250 mV (AC voltage levels) for differential inputs ref 250 mV (AC voltage levels) for differential inputs ref Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity V V ICR ref V IL 002aaa374 = V for LVCMOS inputs ...
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... V/ns o DUT OUT includes probe and jig capacitance. L output dv_f DUT OUT includes probe and jig capacitance. L dv_r output Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity 20 %, unless otherwise specified test point ( 002aaa377 V ...
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... L LVCMOS RESET 0.5V t PLH output waveform 2 RESET input timing V ICR inputs t HL output waveform 1 to clock inputs Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity 20 %, unless otherwise specified test point ( 002aaa500 ...
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... Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to SSTUG32865_1 Product data sheet timing V ICR inputs t LH output waveform 2 clock inputs Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity V V i(p-p) ICR 002aaa503 © NXP B.V. 2007. All rights reserved ...
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... 9.1 13.1 0.65 7.15 11.05 0.15 8.9 12.9 REFERENCES JEDEC JEITA - - - - - - Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity detail 0.08 0.1 0.1 EUROPEAN PROJECTION SOT802-2 y ISSUE DATE 05-06-21 05-07-13 © NXP B.V. 2007. All rights reserved. ...
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... Solder bath specifications, including temperature and impurities SSTUG32865_1 Product data sheet 1.8 V DDR2-1G registered buffer with parity Rev. 01 — 16 August 2007 SSTUG32865 © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 23. Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity Figure 23) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
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... Dual In-line Memory Module Dynamic Random Access Memory Low Voltage Complementary Metal Oxide Semiconductor Registered Dual In-line Memory Module Stub Series Terminated Logic Data sheet status Product data sheet Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity peak temperature Change notice Supersedes - - © ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 16 August 2007 SSTUG32865 1.8 V DDR2-1G registered buffer with parity © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 16 August 2007 Document identifier: SSTUG32865_1 ...