SSTUM32866 NXP Semiconductors, SSTUM32866 Datasheet
SSTUM32866
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SSTUM32866 Summary of contents
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... DDR2-1G RDIMM applications Rev. 01 — 29 June 2007 1. General description The SSTUM32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function defined in accordance with the JEDEC standard for the SSTUM32866 registered buffer. The register is configurable (using confi ...
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... Applications I 400 MT/s to 800 MT/s and higher DDR2 registered DIMMs desiring parity checking functionality 4. Ordering information Table 1. Ordering information Type number Solder process SSTUM32866EC/G Pb-free (SnAgCu solder ball compound) SSTUM32866EC/S Pb-free (SnAgCu solder ball compound) 4.1 Ordering options Table 2. Type number SSTUM32866EC/G SSTUM32866EC/S SSTUM32866_1 Product data sheet 1.8 V DDR2-1G confi ...
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... NXP Semiconductors 5. Functional diagram (1) Disabled configuration. Fig 1. Functional diagram of SSTUM32866 Register A configuration with and SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity RESET CK CK VREF DCKE DODT DCS CSR other channels (D3, D5, D6 D14 (positive logic) Rev. 01 — ...
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... D8 to D14 PARITY CHECK CLK CLK CLK 2-BIT LPS1 COUNTER (internal node) R Rev. 01 — 29 June 2007 SSTUM32866 Q2A, Q3A, Q5A, Q6A, D2, D3, D5, D6, 11 Q8A to Q14A D8 to D14 11 11 Q2B, Q3B, Q5B, Q6B, Q8B to Q14B CLK CLK ...
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... D21 GND GND N D11 D22 D12 D23 GND GND R D13 D24 D14 D25 VREF V DD Rev. 01 — 29 June 2007 SSTUM32866 QCKE DNU Q2 Q15 Q3 Q16 QODT DNU Q5 Q17 Q6 Q18 C1 C0 QCS DNU n.c. n.c. Q8 Q19 Q9 Q20 Q10 Q21 Q11 ...
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... DODT DNU D12 DNU GND GND R D13 DNU DCKE DNU VREF V DD Rev. 01 — 29 June 2007 SSTUM32866 5 6 QCKEA QCKEB Q2A Q2B Q3A Q3B QODTA QODTB Q5A Q5B Q6A Q6B C1 C0 QCSA QCSB n.c. n.c. Q8A Q8B Q9A Q9B ...
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... Not connected. Ball present but no internal connection to the die not use. Inputs are in standby-equivalent mode and outputs are driven LOW. 4, Figure 5, and Figure 6 for ball number. Rev. 01 — 29 June 2007 SSTUM32866 [1] [1] © NXP B.V. 2007. All rights reserved ...
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... Data outputs = Q10, Q12, Q13 when and Functional description The SSTUM32866 is a 25-bit 14-bit configurable registered buffer with parity, designed for 1 2 All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset (RESET) inputs are LVCMOS ...
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... As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUM32866 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. ...
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... < > continuous < V < Human Body Model (HBM); 1 100 pF Machine Model (MM 200 pF Rev. 01 — 29 June 2007 SSTUM32866 = HIGH-to-LOW transition. Outputs [2] [3] PAR_IN PPO even L L odd L H even H H odd ...
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... CSR, and V ref PAR_IN inputs data (Dn), CSR, and - PAR_IN inputs [1] RESET, Cn 0.65 [1] RESET [2] CK, CK 0.675 [2] CK, CK 600 - - operating in free air SSTUM32866EC/G 0 SSTUM32866EC/S 0 Rev. 01 — 29 June 2007 SSTUM32866 Typ Max - 2.0 V 0. 0.040 0.040 ref ref - 0.250 - - - V ...
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... mA 1 data and CSR inputs 250 mV 1 ref DD CK and CK inputs 0.9 V; ICR V = 600 mV 1.8 V i(p-p) DD RESET input GND 1 instantaneous steady-state Rev. 01 — 29 June 2007 SSTUM32866 Min Typ Max 1 0 ...
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... CK and CK to QERR from CK and from RESET to Qn from RESET to PPO from RESET to QERR Table 7), unless otherwise specified. See Conditions from from from Rev. 01 — 29 June 2007 SSTUM32866 Section 11.1. Min Typ Max - - 550 [1][2] ...
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... Timing diagrams RESET DCS CSR D25 Q25 PAR_IN PPO QERR Fig 7. Timing diagram for SSTUM32866 used as a single device SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity ...
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... D14 Q14 PAR_IN PPO QERR (not used) Fig 8. Timing diagram for the first SSTUM32866 ( Register A configuration) device used in pair SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity ...
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... PAR_IN PPO (not used) QERR (1) PAR_IN is driven from PPO of the first SSTUM32866 device. Fig 9. Timing diagram for the second SSTUM32866 ( Register B configuration) device used in pair SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity ...
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... 250 mV (AC voltage levels) for differential inputs ref 250 mV (AC voltage levels) for differential inputs ref Rev. 01 — 29 June 2007 SSTUM32866 20 %, unless otherwise specified. DUT delay = 350 OUT ( 0. ...
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... PLH PHL 250 mV (AC voltage levels) for differential inputs ref 250 mV (AC voltage levels) for differential inputs ref Rev. 01 — 29 June 2007 SSTUM32866 V V ICR ref V IL 002aaa374 = V for LVCMOS inputs. ...
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... V DDR2-1G configurable registered buffer with parity 0 input slew rate = 1 V/ns o DUT OUT includes probe and jig capacitance. L output dv_f DUT OUT includes probe and jig capacitance. L dv_r output Rev. 01 — 29 June 2007 SSTUM32866 20 %, unless otherwise specified test point ( 002aaa377 ...
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... L LVCMOS RESET 0.5V t PLH output waveform 2 RESET input. timing V ICR inputs t HL output waveform 1 to clock inputs Rev. 01 — 29 June 2007 SSTUM32866 20 %, unless otherwise specified test point ( 002aaa500 0.15 V ...
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... ICR CK t PLH output and t are the same PLH PHL 600 mV. i(p-p) inputs Rev. 01 — 29 June 2007 SSTUM32866 V V i(p-p) ICR 002aaa503 20 %, unless otherwise specified. test point ( 002aaa654 V V i(p-p) ICR t PHL ...
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... PLH PHL 250 mV (AC voltage levels) for differential inputs ref 250 mV (AC voltage levels) for differential inputs ref RESET input Rev. 01 — 29 June 2007 SSTUM32866 PHL 002aaa376 = V for LVCMOS inputs ...
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... 5.6 13.6 0 0.15 5.4 13.4 REFERENCES JEDEC JEITA Rev. 01 — 29 June 2007 SSTUM32866 detail 0.1 0.1 0.2 EUROPEAN PROJECTION SOT536-1 ISSUE DATE 00-03-04 03-02-05 © NXP B.V. 2007. All rights reserved ...
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... Solder bath specifications, including temperature and impurities SSTUM32866_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity Rev. 01 — 29 June 2007 SSTUM32866 © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 28. Rev. 01 — 29 June 2007 SSTUM32866 Figure 28) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2007. All rights reserved. ...
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... Low Voltage Complementary Metal Oxide Semiconductor Partial Parity Out Pulse Repetition Rate Registered Dual In-line Memory Module Stub Series Terminated Logic Data sheet status Product data sheet Rev. 01 — 29 June 2007 SSTUM32866 peak temperature 001aac844 Change notice Supersedes - - © NXP B.V. 2007. All rights reserved. ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 29 June 2007 SSTUM32866 © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SSTUM32866 All rights reserved. Date of release: 29 June 2007 Document identifier: SSTUM32866_1 ...