SST34WA3283 Silicon Storage Technology, Inc., SST34WA3283 Datasheet - Page 8

• Manufacturer Part Number: SST34WA3283
• Description: 32 Mbit Burst Mode Concurrent Superflash Combomemory 32 Mbit Burst Mode Concurrent Superflash Combomemory
• Manufacturer: Silicon Storage Technology, Inc.

Advance Information
Memory Architecture
The flash memory of SST34WA32A3/32A4/3283/3284
features a 4-bank, 512 KWord uniform multi-bank
architecture. Either the top or bottom bank consists of 15
standard 32 KWord blocks and four parameter 8 KWord
blocks for added granularity. The remaining three banks
each contain uniform 32 KWord blocks. All 8 and 32 KWord
blocks are further divided into 4 or 16 uniform 2 KWord
sectors, respectively.
Each block and sector can be individually erased for
greater flexibility. The device’s unique bank architecture,
allows reads from any bank while another bank is being
erased (RWE) or programmed (RWP). The device also
supports
programming data in any other sector or block other than
the one being erase-suspended. It can also read data at
any memory sector or block other than the one being
erased during the Erase-Suspend operation. Suspend
operations cannot be nested because the system needs to
complete or resume any previously suspended operation
before a new operation can be suspended.
Sector/Block-Erase Operation
The Sector/Block-Erase operation allows the system to
erase the device on a sector-by-sector or block-by-block
basis. The SST34WA32A3/32A4/3283/3284 offers Sector-
Erase and Block-Erase modes. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode erases either the regular 32 KWord blocks or the
smaller 8 KWord Parameter Blocks. The Sector-Erase
operation is initiated by executing a six-word command
sequence with Sector-Erase command (50H) and sector
address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-word command
sequence with Block-Erase command (30H) and block
address (BA) in the last bus cycle. The Sector or Block
address is latched during the sixth cycle, either on the
rising edge of AVD# or on the falling edge of WE# cycle,
whichever occurs last, while the command (30H/50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. See Figure 14
for timing waveforms and Figure 51 for the flowchart.
©2007 Silicon Storage Technology, Inc.
an
Erase-Suspend
SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284
32 Mbit Burst Mode Concurrent SuperFlash ComboMemory
mode
that
allows
8
Erase-Suspend, Erase-Resume Operations
The Erase-Suspend command temporarily suspends a
Sector/Block-Erase operation which allows data to be read
from any memory location, or to be programmed into any
sector or block that is not suspended for an Erase
operation. The operation is executed by issuing the Erase-
Suspend
automatically enters the Erase-Suspend Read Mode within
TES, 15 µs, after the Erase-Suspend command is issued.
Valid data is read from any sector or block that is not
suspended from an Erase operation. Reading at an
address location within erase-suspended sectors or blocks
will output DQ2 toggling and DQ6 at ‘1’. See Table 6, Write
Operation Status, for details. While in Erase-Suspend
mode, a Word-Program operations are allowed for all
sectors and blocks, with the exception of the sector or block
selected for Erase-Suspend. If a Word Program operation
is attempted in the suspended sector or block, the
command is rejected and the Program operation is not
performed.
The system can also issue the Software ID Entry
command during the Erase-Suspend. After the system has
issued the Software ID Exit command, the device
automatically reverts to Read Mode.
To resume the Sector/Block-Erase operation that is
suspended, the system must issue the Erase-Resume
command. The operation is executed by issuing the Erase-
Resume one-word command, 30H, at any address in the
last word sequence.
For an erase operation being suspended or re-suspended
after resume, the cumulative erase time needed is greater
than the erase time of a non-suspended erase operation.
The accumulative erase time needed may become very
long if the hold time from Erase-Resume to the next Erase-
Suspend operation, T
The Erase-Resume command will be ignored until any
program operations initiated during Erase-Suspend are
complete. The Erase-Suspend and Program Resume
operations have no influence on the program operation.
See Table 5 for details of Suspend-Resume and
Concurrent operations
one-word
ERH
command,
, is less than 330µs.
B0H.
S71358-01-000
The
device
11/07