S25FL128P Meet Spansion Inc., S25FL128P Datasheet - Page 20

• Manufacturer Part Number: S25FL128P
• Description: 128 Megabit Cmos 3.0 Volt Flash Memory With 104 Mhz Spi Serial Peripheral Interface Bus
• Manufacturer: Meet Spansion Inc.

20
11.1.2
Parallel Mode
In parallel mode, the maximum SCK clock frequency is 6 MHz. The device requires a single clock cycle
instead of eight clock cycles to access the next data byte. The memory array output will be the same as in the
serial mode. The only difference is that a byte of data is output per clock cycle instead of a single bit. This
means that 256 bytes of data can be copied into the 256 byte wide page write buffer in 256 clock cycles
instead of in 2,048 clock cycles.
Notes
1. 1st Byte = “03h”.
2. 2nd Byte = Address 1, MSB first (bits 23 through 16).
3. 3rd Byte = Address 2, MSB first (bits 15 through 8).
4. 4th Byte = Address 3, MSB first (bits 7 through 0).
5. From the 5th Byte, SO will output the array data.
6. In parallel mode, the maximum clock frequency (Fsck) is 6 MHz.
7. For parallel mode operation, the device requires an Enter Parallel Mode command (55h) before the READ command. An Exit Parallel
Mode (45h) command or a power-down / power-up sequence is required to exit the parallel mode.
PO[7-0]
SCK
CS#
SI
Figure 11.2 Parallel Read Instruction Sequence
Instruction
High Impedance
D a t a
S25FL128P
S h e e t
( P r e l i m i n a r y )
24-Bit
Address
S25FL128P_00_04 July 2, 2007
Data Out