S25FL128P Meet Spansion Inc., S25FL128P Datasheet - Page 30

• Manufacturer Part Number: S25FL128P
• Description: 128 Megabit Cmos 3.0 Volt Flash Memory With 104 Mhz Spi Serial Peripheral Interface Bus
• Manufacturer: Meet Spansion Inc.

Note
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
11.9
30
WP#/ACC
11.9.1
Signal
1
1
0
0
Page Program (PP: 02h)
Serial Mode
SRWD Bit
Table 11.5
HPM either by setting the SRWD bit after driving WP#/ACC low, or by driving WP#/ACC low after setting the
SRWD bit. However, the device disables HPM only when WP#/ACC is driven high.
Note that HPM only protects against changes to the status register. Since BP2:BP0 (or BP3:BP0) cannot be
changed in HPM, the size of the protected area of the memory array cannot be changed. Note that HPM
provides no protection to the memory array area outside that specified by Block Protect bits (Software
Protected Mode, or SPM).
If WP#/ACC is permanently tied high, HPM can never be activated, and only the SPM (Block Protect bits of
the Status Register) can be used.
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one
data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence
is shown in
The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this
limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256
bytes sent at the starting address of the specified page. This may result in data being programmed into
different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they
are correctly programmed at the requested addresses.
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute a Page Program (PP) command that specifies a page that is protected by the
Block Protect bits (see
1
0
0
1
Software
Protected
(SPM)
Hardware
Protected
(HPM)
shows that neither WP#/ACC or SRWD bit by themselves can enable HPM. The device can enter
Figure 11.14
Mode
Status Register is writable (if the WREN
command has set the WEL bit). The values in
the SRWD, BP2, BP1 and BP0 (or BP3, BP2,
BP1 and BP0) bits can be changed.
Status Register is Hardware write protected.
The values in the SRWD, BP2, BP1 and BP0
(or BP3, BP2, BP1 and BP0) bits cannot be
changed.
Table 7.1 on page
Write Protection of the Status Register
and
Table
Table 11.5 Protection Modes
D a t a
11.6.
S25FL128P
S h e e t
13).
( P r e l i m i n a r y )
Table 7.1 on page
Protected against program
Protected against program
and erase commands
and erase commands
Protected Area
(See Note)
13.
S25FL128P_00_04 July 2, 2007
PP
. The Status Register may
Program and Sector Erase
Program and Sector Erase
Ready to accept Page
Ready to accept Page
Unprotected Area
(See Note)
commands
commands