S25FL040A Meet Spansion Inc., S25FL040A Datasheet - Page 22

• Manufacturer Part Number: S25FL040A
• Description: Small Sector For Boot And Parameter Storage 4-megabit Cmos 3.0 Volt Flash Memory With 50 Mhz Spi Bus Interface
• Manufacturer: Meet Spansion Inc.

9.8
22
Write Status Register (WRSR)
on page
Protected mode is enabled, BP2:BP0 cannot be changed. The Bulk Erase (BE) command is executed only if
all Block Protect (BP2, BP1, BP0) bits are 0.
Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write
Protect (W#) signal. When SRWD is set to 1 and W# is driven low, the device enters the Hardware Protected
mode. The non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the
device ignores any Write Status Register (WRSR) command.
The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable
(WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to
writing the WRSR command.
The host system must drive CS# low, write the WRSR command, and the appropriate data byte on SI
(Figure
The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must
be used for that purpose. Bit 0 is a status bit controlled internally by the Flash device. Bits 6 and 5 are always
read as 0 and have no user significance.
The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit
and W# together place the device in the Hardware Protected Mode (HPM). The device ignores all WRSR
commands once it enters the Hardware Protected Mode (HPM).
and the SRWD bit must be 1 for this to occur.
Note
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 9.4
either by setting the SRWD bit after driving W# low, or by driving W# low after setting the SRWD bit.
However, the device disables HPM only when W# is driven high.
Signal
W#
1
1
0
0
9.8).
SRWD
13) is protected against Page Program (PP) and Sector Erase (SE) commands. If the Hardware
Bit
1
0
0
1
shows that neither W# or SRWD bit by themselves can enable HPM. The device can enter HPM
Software
Protected
(SPM)
Hardware
Protected
(HPM)
Mode
SCK
CS#
SO
SI
Figure 9.8 Write Status Register (WRSR) Command Sequence
Mode 3
Mode 0
Hi-Z
Status Register is writable (if the WREN
command has set the WEL bit). The values in
the SRWD, BP2, BP1 and BP0 bits can be
changed.
Status Register is Hardware write protected.
The values in the SRWD, BP2, BP1 and BP0
bits cannot be changed.
Write Protection of the Status Register
Table 9.3 on page 21
0
1
S25FL040A
Table 9.4 Protection Modes
2
Command
3
D a t a
4
5
shows the status register bits and their functions.
6
S h e e t
7
MSB
7
8 9 10 11 12 13 14 15
6
Protected against program
Protected against program
Status Register In
5
Table 9.4
and erase commands
and erase commands
Protected Area
4
(See Note)
3
2
shows that W# must be driven low
1
S25FL040A_00_B2 July 2, 2007
0
Table 7.1 on page
Program and Sector Erase
Program and Sector Erase
Ready to accept Page
Ready to accept Page
Unprotected Area
(See Note)
commands
commands
13.